Shift Register synthesis??

Hi, while i was synthesizing a simple shift register i got an odd behavior. The device i'm using is a virtex2pro (xc2vp2) the verilog i've used is:

module shift_reg(clk, in , out); parameter DIM=16; input clk, rst, in; output out;

reg [DIM-1:0] SR;

always@(posedge clk) SR

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I can't comment on the reported frequency but the LUT-based SRL does not support reset. There is no circuitry to change the stored SRL values to a reset state at the assertion of a reset signal. So, if you want the contents of the SRL to go to a reset state, you must implement the SRL in registers (or - more appropriately - the tool should do so for you).

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The LUT as shift register application is not optimized for timing and it doesn't support reset or when you add the reset you get the actual flops. If these flops are placed nicely, ie with minimal routing delay the minimum period is decided by the equation Tclk2Q + Tsetup (assuming no-clock tree skew) so it's reasonable to get a number around 1ns for this. The reported register to lut to register performance of a -6 device is 1046 MHz.

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hi, I suggest you to see the XST user guide 8.1i (page 93) for more details, there they say because of the reset, your shift register can't be synthetised as Lut configured as shift register .

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Without any speed or area constraints, I expect that synthesis fit your first version into an SRL with slower flops. The second version would not fit an SRL so you got real flops, which are faster more portable, and easier to simulate. Unless you are real short on flops, I would leave it that way.

-- Mike Treseler

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Mike Treseler

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