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Parallel readback on Spartan IIE

Hi All,

Having a few problems implementing readback on a Xilinx SpartanIIE device. We have a uP programming via the parallel port, this works OK. However, the documentation and timing diagrams for parallel readback seem to be a little sketchy. It seems that data is both captured by the SpartanIIE on a rising CCLK edge, and also clocked out on a rising CCLK edge. I assume this means we should latch our data maybe on the falling edge when reading? Anyone got parallel readback to work?

Thanks,

Mark.

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markp
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Reply to
Aurelian Lazarut

I want to be able to continually check the FPGA to verify the logic hasn't been changed or corrupted in any way e.g. hard errors, radiation induced errors etc.. This is primarily to satisfy a customer's concern. It should be possible to read back the configuration (after masking the relevant bits) and check it's still intact.

Mark.

Reply to
markp

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