Field-Programmable Gate Arrays

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help!! my modelsim occur error on strting

i am korean student studying for fpga I try use modelsim but occur error on starting! help me plz~ my system is windows...
0 comments posted 20yrs
posted by idkiller
0 comments posted 20yrs posted by idkiller

Spartan 3E 500 DCM fine phase shift doesn't work

Hello, I have a problem with the Spartan 3E DCMs: I use two DCMs with the following configuration: - input clk = 50 MHz...
0 comments posted 20yrs
posted by Karel.Deprez
0 comments posted 20yrs posted by Karel.Deprez

SerialATA with Virtex-II Pro

I've got a dev.board from Digilent (XUPV2P, [1]) with an Xilinx Virtex-II Pro (XC2VP30, to be exact). I've been reading...
16 comments posted 20yrs
posted by tlan
16 comments posted 20yrs posted by tlan

CCLK does not start up on boot

Hi all, I am trying to program a Spartan3 device. I can program the FPGA and it works.As well I can program the PROM. B...
1 comments posted 20yrs
posted by svasus
1 comments posted 20yrs posted by svasus

PowerPC Problems in Virtex

Hi folks, I am experiencing problems with my PowerPC design for a P50. The PowerPC consist of a simple for loop where i...
2 comments posted 20yrs
posted by eziggurat
2 comments posted 20yrs posted by eziggurat

SDRAM controller selection

Hello grps, Can you tell me what is the basis for selecting the DDR controller? For example i have a micron DDR SDRAM a...
1 comments posted 20yrs
posted by praveenkumar.bm
1 comments posted 20yrs posted by praveenkumar.bm

Using the IEEE Std 1532

Hi All, I would like to know when should I use the IEEE 1532 files. I found that "Users will now be able to program cha...
1 comments posted 20yrs
posted by nemesis_nyx
1 comments posted 20yrs posted by nemesis_nyx

risc processor in altera up3 kit

hello everyone..iam newbie to the world of fpga's..can anyone sugges something frm where i can start my foray in to thi...
2 comments posted 20yrs
posted by anvesh
2 comments posted 20yrs posted by anvesh

Debugging ideas.

Hi all, I am having problems debugging my memory controller. My initial idea is to capture a frame and display the same...
7 comments posted 20yrs
posted by subhasri.krishnan
7 comments posted 20yrs posted by subhasri.krishnan

Urgent Help Needed!!!!!

Hi Friends Friends, i have been struggling for 1.5 months on a problem.Let me explain u a little bit. I am working on F...
51 comments posted 20yrs
posted by coolsaroj
51 comments posted 20yrs posted by coolsaroj

Where are FPGA heading?

Reading the LSI Strucutred ASIC fiasco thread has made me think. People are saying the FPGA revenues are going to grow,...
40 comments posted 20yrs
posted by brakepiston
40 comments posted 20yrs posted by brakepiston

ISE 8.1 linux 64bit license key

Hi all, I've installed ISE 8.1 for linux (32 bit) on a Debian machine with no pain at all, it works fine. Now I'm tryin...
3 comments posted 20yrs
posted by marcobuffa
3 comments posted 20yrs posted by marcobuffa

ADC Interleaving

I am considering trying to interleave two 250MS/s ADCs. Would this be good idea? possible? or too much trouble? Cheers J...
4 comments posted 20yrs
posted by maxascent
4 comments posted 20yrs posted by maxascent