Field-Programmable Gate Arrays

Spartan 3E 500 DCM fine phase shift doesn't work

Hello, I have a problem with the Spartan 3E DCMs: I use two DCMs with the following configuration: - input clk = 50 MHz...

0 comments posted 20yrs

posted by Karel.Deprez

0 comments posted 20yrs posted by Karel.Deprez

SerialATA with Virtex-II Pro

I've got a dev.board from Digilent (XUPV2P, [1]) with an Xilinx Virtex-II Pro (XC2VP30, to be exact). I've been reading...

16 comments posted 20yrs

posted by tlan

16 comments posted 20yrs posted by tlan

CCLK does not start up on boot

Hi all, I am trying to program a Spartan3 device. I can program the FPGA and it works.As well I can program the PROM. B...

1 comments posted 20yrs

posted by svasus

1 comments posted 20yrs posted by svasus

replacement of opb_mdm core for ML401 kit: opb_mdm_v2_01_a

Hi there. I am testing out the WebServer demo for the ML403 card on a ML401. When I try to connect to the card with the...

1 comments posted 20yrs

posted by raybakk

1 comments posted 20yrs posted by raybakk

Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file

II would like to find out what is the most sensible way to generate a text output file with timing measurements from a...

4 comments posted 20yrs

posted by peter

4 comments posted 20yrs posted by peter

PowerPC Problems in Virtex

Hi folks, I am experiencing problems with my PowerPC design for a P50. The PowerPC consist of a simple for loop where i...

2 comments posted 20yrs

posted by eziggurat

2 comments posted 20yrs posted by eziggurat

SDRAM controller selection

Hello grps, Can you tell me what is the basis for selecting the DDR controller? For example i have a micron DDR SDRAM a...

1 comments posted 20yrs

posted by praveenkumar.bm

1 comments posted 20yrs posted by praveenkumar.bm

Using the IEEE Std 1532

Hi All, I would like to know when should I use the IEEE 1532 files. I found that "Users will now be able to program cha...

1 comments posted 20yrs

posted by nemesis_nyx

1 comments posted 20yrs posted by nemesis_nyx

risc processor in altera up3 kit

hello everyone..iam newbie to the world of fpga's..can anyone sugges something frm where i can start my foray in to thi...

2 comments posted 20yrs

posted by anvesh

2 comments posted 20yrs posted by anvesh

Debugging ideas.

Hi all, I am having problems debugging my memory controller. My initial idea is to capture a frame and display the same...

7 comments posted 20yrs

posted by subhasri.krishnan

7 comments posted 20yrs posted by subhasri.krishnan

Urgent Help Needed!!!!!

Hi Friends Friends, i have been struggling for 1.5 months on a problem.Let me explain u a little bit. I am working on F...

51 comments posted 20yrs

posted by coolsaroj

51 comments posted 20yrs posted by coolsaroj

Where are FPGA heading?

Reading the LSI Strucutred ASIC fiasco thread has made me think. People are saying the FPGA revenues are going to grow,...

40 comments posted 20yrs

posted by brakepiston

40 comments posted 20yrs posted by brakepiston

ISE 8.1 linux 64bit license key

Hi all, I've installed ISE 8.1 for linux (32 bit) on a Debian machine with no pain at all, it works fine. Now I'm tryin...

3 comments posted 20yrs

posted by marcobuffa

3 comments posted 20yrs posted by marcobuffa

ADC Interleaving

I am considering trying to interleave two 250MS/s ADCs. Would this be good idea? possible? or too much trouble? Cheers J...

4 comments posted 20yrs

posted by maxascent

4 comments posted 20yrs posted by maxascent

Purchasing Virtex-4 FPGAs

Hi, I'm looking for a way to purchase V-4 (more specifically V4FX20 and V4FX40) at very low quantities (4-5 devices). I...

2 comments posted 20yrs

posted by gpouikli

2 comments posted 20yrs posted by gpouikli