I am experiencing problems with my PowerPC design for a P50. The PowerPC consist of a simple for loop where it polls a custom OPB peripheral. When the software starts executing, I seem to get errors in the data from the polling function. I have added a ChipScope core and the waveform seems to indicate the reset seem to be flunctuating and this seem to indicate the DCM is maybe not locked properly or reset is actually flunctuating. The strange thing is that I have a signal which is the inverse of reset but the waveform does not seem to show it.
I have step through the software using XMD and added a breakpoint within the function in GDB, and the software works fine and data is not corrupted but when I ran it the second time round, I get a SIGTRAP error in the debugger and the data in ChipScope and UART shows the data is corrupted and the reset signal fluctuating. I have scan thorugh the code and cannot see any problems with the code and the project, and also check the stack and the heap but I am allocating 128K of BRAM and the code is just a simple for loop with some drivers function. I am not using malloc in the code.
The other thing is the design works fine for P70 and I have tried it in several boards with a P70, and also the code use for testing the P70 consist of more than 20 OPB peripherals whilst this code is just 2 peripherals.
Any help will be great.
Cheers Paul Lee