Latest threads in Field-Programmable Gate Arrays

Start Your Free Blog

Hi, I setup an account at http://www.bloggerteam.com the site provides quality blog hosting services with quality edita...

0 20yrs

webconf

0 20yrs webconf

FPGA FIR advice

Hello, I never actually implemented FIR filters in FPGAs. But, if I am able to assume, I would say that FIR filters tak...

11 20yrs

rover8898

11 20yrs rover8898

memories for virtex-4 and Spartan-3E

Hi all, i am looking for VHDL instantiation of BRAMs and LUT memories .i copied those instantiations from libraries of...

1 20yrs

bachimanchi

1 20yrs bachimanchi

Free Manpower Recruitment Service for Recent Graduate FPGA Engineers Visit www.fpgasps.com

1 20yrs

fpgasps

1 20yrs fpgasps

Free Receuitment Service for Recent Graduate FPGA Engineers

Free Receuitment Service for Recent Graduate FPGA Engineers Visit www.fpgasps.com for more detailts

0 20yrs

fpgasps

0 20yrs fpgasps

Spartan-3E Sample Pack

I realize that all the 'freebees' are long gone now, but are there any vendors selling them? Or something *really* simi...

4 20yrs

ziggy

4 20yrs ziggy

PCI Configuration access and Target State Machine...

How is a PCI target FSM related to a configuration read/write? Considering that FRAME# is asserted for one clock cyle o...

10 20yrs

adventleaf

10 20yrs adventleaf

microprocessor design: where to go from here?

Hello everyone In the last couple of months, I have become very interested in CPU design. Specially the ones that you c...

4 20yrs

burn.sir

4 20yrs burn.sir

Progress bar in ISE 8.1

It was there in ISE 7.1 but now I've upgraded to ISE 8.1 SP2 and it's gone. What's happened to it? It's even more diffi...

0 20yrs

fred

0 20yrs fred

Have you ever considered of mousing ambidextrously?

I'm also a programmer, as working in front of computer day and day, my right hand is so tired and get some pain. So I t...

1 20yrs

WangQiangg

1 20yrs WangQiangg

Does support Partial Reconfiguration FPGA other companies except for Xilinx?

I write a diploma on Partial Reconfiguration. Noticed circumstance that Partial Reconfiguration is used only on Xilinx F...

4 20yrs

valerios

4 20yrs valerios

Virtex-4 BRAM control signal inversion

Hi all, In the Virtex-4 UG (ug070.pdf) page 121 it's clearly written that it's possible to inverse the control pins (ac...

1 20yrs

taileb.mehdi

1 20yrs taileb.mehdi

Can one use MGT clock input for global clock in Virtex4

I think I read somewhere that it is possible, but can't find it now... I tried assigning the pins in ucf, but map failed...

2 20yrs

mbmsv

2 20yrs mbmsv

question regarding LUT and MAP

Hi, I have a design where I'm trying to test LUT. I have a normal BIST application which has a counter feeding addresse...

1 20yrs

sarnaths

1 20yrs sarnaths

question regarding maximum frequency on virte-e-2000

Hi all, i am designing a circuit for a cryptogrpahy application based on elliptic curve cryptography.I want to know one...

1 20yrs

bachimanchi

1 20yrs bachimanchi

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