Virtex-4 BRAM control signal inversion

Hi all, In the Virtex-4 UG (ug070.pdf) page 121 it's clearly written that it's possible to inverse the control pins (active high or low) but I failed to find how. In the list of the BRAM primitive attributes (P122) there is no mention of any attribute which permits these inversions.

Thanks in advance for answers. Cheers


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Although I haven't designed with the Virtex-4 explicitly (mine have been Virtex series II and prior, Spartan 2, 2E, 3, 3E) The inversion is

*probably* done automatically for the control signals (not the address or data) through a dedicated mux for normal or inverted logic as the signal enters the BlockRAM. This will not be done through an attribute but through the logic optimization process.

Just use inverted logic and note that your results don't add an extra inverter in your completed logic path.

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