question regarding LUT and MAP


I have a design where I'm trying to test LUT. I have a normal BIST application which has a counter feeding addresses to an LUT. I'm trying to test the LUT for faults basically, so I load in some sort of a test pattern into the LUT. I compare the output of two LUTs to determine if there is a fault. My comparator is also an LUT (since there are

4-inputs, two from the Y and two from the X outputs of a Spartan II slice).

What I have noticed is that when I try to implement this design through Xilinx ISE, the MAP process does not consider the LUTs under test and thus removes them from the design. However, for my work, it is imperative that these LUTs not be removed. I tried running the MAP program with the -u option, but that doesn't help either.

Has anybody encountered this before? And if so, do you have any suggestions on how to ensure that my circuit-under-test LUTs do not get trimmed?

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To "keep" logic from being combined, i.e., to "keep" signals from disappearing, try using the "KEEP" attribute. In vhdl:

attribute keep : string; attribute keep of signal_name: signal is "true";

HTH, John

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