FPGA FIR advice

I disagree in several ways:

2. 0 FFs are not much anymore, when FPGAs have tens and even hundreds of thousands of FFs.
3. Modern FPGAs have dedicated multipliers and accumulators that are very fast
4. FPGAs are fast,but often the application does not need that speed, and then the complexity (cost) can be reduced by time-multipexing. Peter Alfke, Xilinx Applications

I disagree in several ways:

2. 0 FFs are not much anymore, when FPGAs have tens and even hundreds of thousands of FFs.
3. Modern FPGAs have dedicated multipliers and accumulators that are very fast
4. FPGAs are fast,but often the application does not need that speed, and then the complexity (cost) can be reduced by time-multipexing. Peter Alfke, Xilinx Applications

20 Tap FIR filters don't occupy all that much room in FPGAs, especially the modern parts which have quite a bit more logic resources than earlier chips. First, most times we can run the clock at a multiple of the sample rate, which allows us to time share the hardware either by using the same multiplier for several tap coefficients, or by using several clock cycles to accomplish the multiplies (distributed arithmetic takes that a step further to postpone the shift-adds). A brute force full parallel implementation will be the largest, but for 20 taps, even that is not all that large, especially if you take advantage of the embedded multipliers present in most of the current families. Look at the multipliers and distributed arithmetic pages on my website for a bit of a tutorial: http//:

Hi Ray and Peter,

I am sorry for hijacking your thread Roger , but I think my question is relevant.

I was thinking of using about 8 FIR (bandpass) filters in parallel to create a graphic equalizer. Now I know there are some phase problems with this method but it seems to me like a very logical way to go about this problem. I was wondering if you guys know of any better methods?

I also was thinking of using 16 taps each.

320 FF's is not a lot actually. My XC3S200 (which is probably dirt cheap) has almost 4000 FF's. Enough for your filter network and much more.

-Isaac

Another great advantage to FPGA FIRs: most of the time the FIRs are symmetric which allows half the taps (half the multipliers) to implement the full FIR by adding t-? to t+? before multiplying by the common coefficient, the implementation is more elegant.

Hi John,

I cannot see what you mean? Can you offer a quick example?

-Isaac

An FIR filter is implemented as a dot product of a constant vector and a vector made up of the input samples delayed,

y[n] = c[0].x[n] + c[1].x[n-1] + ... c[m-1].x[n-m+1] for an m tap filter.

The c[n] are the coefficients. If the filter has a linear phase response, the coefficients are symmetric, so c[0] = c[m-1], c[1] = c[m-2], etc.

We can group the expression for y[n] as follows:

y[n] = c[0].(x[n] + x[n-m+1) + c[1].(x[n-1] + x[n-m+2]) + ...

This has (roughly) halved the number of multipliers. I say roughly, because m is often odd.

Regards, Allan

Ahh, I see, thanks.

Do you guys know of a good filter design software, I have an old one for DOS, but it is quite difficult to use (Also I do not have access to MATLAB).

-Isaac

Hi Isaac,

You could try Altera's FIR Compiler. Even if you don't have a license for generating the actual FIR cores it still generate the coefficients for you, allows you to compare real-vs-discrete characteristics, see the effects of windowing etc.

Ben

On a sunny day (20 Mar 2006 10:59:37 -0800) it happened "Isaac Bosompem" wrote in :

Also runs in Linux windows emulator wine.

There are several more, remez (Linux), but this one is free and has usable GUI, not a lot of silly limitations. Have only played with it a little bit, but maybe you like it.

One of the tools I use is Scopefir, which is a FIR filter design tool.

For the money, it is a good value.