Hi, We are developing a product that passes data between an xDSL interface and a proprietory optical interface. We are using a Spartan 3 FPGA. The xDSL chipset generates an 8.192MHz clock that is recovered from the DSL line. (The xDSL chipset uses a digital phase locked loop for this). The current FPGA design uses this clock internally, and uses it to clock the optical interface also. Single clock domain, nice.
However, there is now a requirement to clock the optical interface at a higher rate. How to generate this clock? Xilinx DCM Frequncy Synthesizer would seem to be the obvious choice. However the DCM jitter tolerance requirements are the order of +-1ns period jitter and +-300ps cycle-cycle jitter. I'm very worried the xDSL 8.192MHz clock will exceed this jitter tolerance. The xDSL chipset doesn't specify any jitter characteristics, and anyhow its likely dependent on the characteristics of upstream DSL equipment. So I have ruled out this path as too risky. The DCM jitter tolerance feels like quite a limitation of the DCM so probably I'm not understanding how I can make use of the DCM's in my application.
Does anyone have any hints of practicle FPGA techniques for generating a higher clock? A doubling of the clock frequency would be enough. Just the name of a technique would be enough to get me googling...
The xdsl chipset also has a local oscillator at 22MHz - but it just free runs of course...I could invisage a plesiosynchronous scheme where the optical link runs at 22MHz and I bit stuff to get the required data rate. But it feels too complex, overkill. And then I have to think more carefully about the optical link clock recovery at the far end.
(Keeping the number of clock domains to a minimum is of course a desireable goal).
Regards Andrew