Hi All,
My design flow includes a top-level schematic into which I place symbols which represent lower-level modules, including coregen cores (ISE7.1).
I have modified the schematic symbols for things like adders, multipliers etc, to look like symbols typically found in arithmetic texts.
Now, when one of the coregen core's' parameters are changed (say a bus width) and the core is re-generated, the symbol for that core in my schematic reverts to the nasty rectangle.
How can I avoid this, ie. how do I avoid having to re-draw my symbols every time I change core parameters or add a port (say a ACLR) ?
Hope someone can help - seems like this should be possible.
Cheers, PeterC.