Linux on ml403

Can you post your boot messages?

Hi, Here is the trace when using the kernel 2.4 devel

Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc. ( snipped-for-privacy@mvista.com) On node 0 totalpages: 16384 zone(0): 16384 pages. zone(1): 0 pages. zone(2): 0 pages. Kernel command line: console=ttyS0,9600 root=/dev/xsysace/disc0/part3 rw Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFE000 Calibrating delay loop... 99.73 BogoMIPS Oops: kernel access of bad area, sig: 11 NIP: 00000000 XER: 0000005E LR: 00000000 SP: C0182E50 REGS: c0182da0 TRAP: 0400 Not tainted MSR: 00001030 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 11 TASK = c0181020[0] 'swapper' Last syscall: 0 last math 00000000 last altivec 00000000 GPR00: 00000000 C0182E50 C0181020 C0181020 00000000 00000001 C0181120

00000048 GPR08: 00000048 00000000 00000000 00000017 24000022 0000CC60 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 00001032 00182ED0 00000000 C0000000 GPR24: C019DDB0 00000001 C01A0000 C01A0000 044AA234 00000001 00000000 C0181020 Call backtrace: 00000000 C001C27C C0005F30 C00047C0 C0196064 C01943B8 C019154C C0002328 Kernel panic: Aiee, killing interrupt handler! In interrupt handler - not syncing Rebooting in 180 seconds..

I have also just tried to use xmon in the kernel which indicates a kernel stack overflow (?!?). If this can be of any help understanding the problem.

Best regards,

JF Hasson

...

In the above, what is "mapped to 0xFDFFE000"?

If it's the interrupt vector table, be aware that the register pointing to it is only 16 bits wide, holding the 16 MSBs. So the vectors are at FDFFE000 but the PPC interrupt logic looks for them at FDFF0000.

This doesn't seem to be very clearly documented.

Apologies if this has nothing to do with the problem you are experiencing...

- Brian

Hi, I know this is a bad hack, but just disable the Xilinx INT controller for now and then compile the kernel. After compiling the kernel, please try downloading... I guess doing this way would atleast narrow down the problem...

-- Parag

Jean-Francois,

follow the instructions in the ML403 Reference Design Users Guide (pg

39). In particular, create the board support package with the Linux MLD and use the patch_linux script in the linux sub-directory of the ML403 reference design. The patch sets bits 1 and 3 in CCR0 which is required for ES silicon, i.e. silicon where the PPC405 has a PVR of 0x20011430. After applying the patch the problem will be gone.

- Peter

Links:

- ML403 Web Page:

- ML403 Users Guide:

- ML403 reference design:

jfh wrote:

Hi,

Thank you all for the answers. I will try the advice of using the patch delivered by Xilinx which I wasn't aware of.

JF Hasson