Field-Programmable Gate Arrays

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LVDS in Cyclone-II

Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II...
13 comments posted 20yrs
posted by johnhandwork
13 comments posted 20yrs posted by johnhandwork

design flow xilinx ise 7.1+synplify pro8.4

Hi, While porting hdl codes in xilinx, I synthesized using synplify with my constraints.Then I place& routed in xilinx-...
0 comments posted 20yrs
posted by prakash.na
0 comments posted 20yrs posted by prakash.na

opensource vs commercial

Hi, I've one basic doubt. If suppose I use opensource processor like leon/openrisc am I reducing my BOM as processor is...
0 comments posted 20yrs
posted by prakash.na
0 comments posted 20yrs posted by prakash.na

Data Validity and Freshness

Hi all, I am trying to interface a ADC with FPGA through SPI interface. FPGA will have SPI slave implemmented. Once i r...
1 comments posted 20yrs
posted by fpgalearner
1 comments posted 20yrs posted by fpgalearner

Delay value for FDDRCPE in Virtex-II Pro FGPA

Hi, I found that the delay value of the element FDDRCPE is 100 ns after running a timing simulation. Is it supposed to...
3 comments posted 20yrs
posted by milindt
3 comments posted 20yrs posted by milindt

Compressing DVI stream

Hi, I want to know what approach you would recommend to compress an incoming DVI data stream (data width 24 bit, pixel...
6 comments posted 20yrs
posted by ALuPin
6 comments posted 20yrs posted by ALuPin

I2C bus controller Implementation

Hello, My name is Julien, I work as Design engineer in France. I am currently implementing in Verilog an I2C controller...
1 comments posted 20yrs
posted by lochen
1 comments posted 20yrs posted by lochen

Xilinx java application freeze

Hello, I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and I'm having a really big problem. Basically every...
5 comments posted 20yrs
posted by SomeOne
5 comments posted 20yrs posted by SomeOne

max lvds IO speed on V2Pro

Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datas...
1 comments posted 20yrs
posted by t
1 comments posted 20yrs posted by t

done pin didn't go high

Hi, I'm working on a board of V2P70 and a flash memory. I didn't have any problems programming the FPGA however all of...
6 comments posted 20yrs
posted by hbolukbasi
6 comments posted 20yrs posted by hbolukbasi