1. Home
  2. Field-Programmable Gate Arrays
  3. Delay value for FDDRCPE in Virtex-II Pro FGPA

Delay value for FDDRCPE in Virtex-II Pro FGPA

Hi,

I found that the delay value of the element FDDRCPE is 100 ns after running a timing simulation.

Is it supposed to be so high? (to confirm it, I also ran a separate simulation of this single element and with different clk frequencies)

FDDRCPE is "Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear", used when interfacing DDR with FPGA. It is present in the simlibs library.

I'm using ISE 8.1 (and found the same thing in 7.1 too)

If it is supposed to be that high, what may be the reason behind it?

See a related post here:

formatting link

Thanks and Regards, Milind

Reply to
Milind
Loading thread data ...
100ns is 10 MHz. This isn't correct. What do you see that tells you "100 ns?" ...tool, verbiage.

formatting link

Reply to
John_H
100 ns is the propagation delay after which the FDDRCPE output changes when inputs are applied.

This is observed in the timing simulation in the Modelsim..

The output of FDDRCPE doesn't change for that initial delay (around 104 ns to b precise), eventhough valid inputs are applied..And all the subsequent changes at the inputs get reflected after that much delay..

I'm also openning a webcase to get the answer..

John_H wrote:

formatting link

Reply to
Milind

sorry the delay in timing simulation was due to

default value of ROC_WIDTH

It was like this in the timesim.vhd: X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR);

Actual delay of the element is 4 ns.

Reply to
Milind

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.