Hi all,
I am trying to interface a ADC with FPGA through SPI interface. FPGA will have SPI slave implemmented. Once i receive the data from ADC i am required to have some kind of data validity and freshness check. One way to check validity is to have data parity embedded with data but ARE THERE ANY OTHER OPTIONS because parity is prone to bit(s) error. Also i am required to have some logic for freshness. Please any suggestions or directions will be apperitiated.
Thanks.