Field-Programmable Gate Arrays

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rather simple gsr Q

Hello all, I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE Project navigator to design the FPGA)....
10 comments posted 20yrs
posted by rover8898
10 comments posted 20yrs posted by rover8898

OPB master

Hi everyone, I am trying to write obout 66MB/s of data to DDR memory (which is connected to OPB bus) conneted to Virtex...
8 comments posted 20yrs
posted by ales.gorkic
8 comments posted 20yrs posted by ales.gorkic

gameboy camera to FPGA

anyone played with connecting GB camera to an FPGA? Rich
2 comments posted 20yrs
posted by aiiadict
2 comments posted 20yrs posted by aiiadict

Virtex-4 Gigabit Ethernet design

Hi I'm evaluating one Gigabit Ethernet design who use the hard Temac embedded in the Virtex-4 FX (ML403 evaluation boar...
12 comments posted 20yrs
posted by david.quinones
12 comments posted 20yrs posted by david.quinones

XUPv"P DDR failure log

hi, I just carried out BIST test on the XUPV2P board and I have been running the memory test several times and still ge...
2 comments posted 20yrs
posted by paul.sw.lee
2 comments posted 20yrs posted by paul.sw.lee

Altera Talkback

I have the full license for Quartus and can't compile a simple project targeting the GX device until I enable the talkb...
2 comments posted 20yrs
posted by lecroy7200
2 comments posted 20yrs posted by lecroy7200

Xst warning, dangling RAMB16B output

hi, In my design on a Spartan-3 I use a number of block RAMs. In most of them, I have a few ports unconnected, but in o...
1 comments posted 20yrs
posted by usenet+5
1 comments posted 20yrs posted by usenet+5

Bizarre behaviour by Quartus?

I'm using Verilog with the Altera Cyclone II / Nios II) development kit. I'm not yet very experienced with FPGAs. My pr...
10 comments posted 20yrs
posted by MikeShepherd564
10 comments posted 20yrs posted by MikeShepherd564

ddr in virtex2

hello folks, i'm working with a avnet board that has a xc2v1500 and i've been trying to use the ddr memory it has. i ca...
1 comments posted 20yrs
posted by rfonteboa
1 comments posted 20yrs posted by rfonteboa

Inferring SRL in Xilinx FPGA

I registered a 37-bit signal using an always block in verilog without reset specification, hoping that a SRL would be i...
5 comments posted 20yrs
posted by rohit2000s
5 comments posted 20yrs posted by rohit2000s

audio codec on the virtex-ii pro board

Is the audio codec on the virtex-ii pro board a good choice for real-time audio processing? I designed an application t...
0 comments posted 20yrs
posted by dasani8888
0 comments posted 20yrs posted by dasani8888

GOF, Enhanced verilog RTL debug.

GOF, Gates On the Fly, version 2.100 has enhanced verilog RTL debug capability. .Verilog RTL browser. .List the design...
0 comments posted 20yrs
posted by nandigits
0 comments posted 20yrs posted by nandigits

Difference in output between testbench and chipscope

Hi all, I made a small fifo module to do some testing. code: http://vis.uky.edu/~sub/Fifotest_Code.doc I first did post...
3 comments posted 20yrs
posted by subhasri.krishnan
3 comments posted 20yrs posted by subhasri.krishnan

RocketIO MGT Clocking Arrangement!

Dear All, I am a little confused with regards to the clocking arrangement associated with the Xilinx Rocket IO MGT. I w...
2 comments posted 20yrs
posted by simon.stockton
2 comments posted 20yrs posted by simon.stockton

initializing arrays with Verilog and XST

All- If I have an array of registers like: reg [3:0] reg_array [3:0]; how to initialize elements with different values?...
4 comments posted 20yrs
posted by jbrower
4 comments posted 20yrs posted by jbrower