hi,
In my design on a Spartan-3 I use a number of block RAMs. In most of them, I have a few ports unconnected, but in only one of them I get a warning:
DesignRules:332 - Blockcheck: Dangling RAMB16B output. Pin DOPB0 of comp ram is not connected.
The RAM is used across 2 clock domains, and is only read on port A, and only written on port B. For this reason, inputs on port A are unconnected, as well as outputs on port B.
here's the instantiation:
RAMB16_S9_S9 ram( .WEA(1'b0), .ENA(en_a), .SSRA(init), .CLKA(clock_a), .ADDRA(addr_a), .DOA(out_a[7:0]), .DOPA(out_a[8]),
.WEB(we_b), .ENB(we_b), .SSRB(1'b0), .CLKB(clock_b), .ADDRB(addr_b), .DIB(in_b[7:0]), .DIPB(in_b[8]) );
The strange thing is that other block RAMs in the same design, that are used in similar ways (although not identical), don't elicit any warnings, even though the same output ports are unconnected.
I'm using XST, ISE Webpack 6.2
Everything works fine, but I'd like to get rid of the warning that's cluttering up the output.