XUPv"P DDR failure log

I have used this test with Kinston RAM (512MB) that I bought from the digilent website. I remeber that I had to get some settings correct in the constraints file and the mhs file before RAM would work correctly. IF I remember correctly, the phase shift on the DCM for the DDR had to be changed. Here are my settings:

#INST "dcm_1/dcm_1/DCM_INST" CLKOUT_PHASE_SHIFT = "FIXED"; #INST "dcm_1/dcm_1/DCM_INST" PHASE_SHIFT = "60";

BEGIN plb_ddr PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 PARAMETER HW_VER = 1.11.a PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_NUM_BANKS_MEM = 2 PARAMETER C_NUM_CLK_PAIRS = 4 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 20000 PARAMETER C_DDR_TWR = 20000 PARAMETER C_DDR_TRAS = 60000 PARAMETER C_DDR_TRC = 90000 PARAMETER C_DDR_TRFC = 100000 PARAMETER C_DDR_TRCD = 30000 PARAMETER C_DDR_TRRD = 20000 PARAMETER C_DDR_TRP = 30000 PARAMETER C_DDR_TREFC = 70300000 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_DDR_DWIDTH = 64 PARAMETER C_DDR_CAS_LAT = 3 PARAMETER C_MEM0_BASEADDR = 0x00000000 PARAMETER C_MEM0_HIGHADDR = 0x0fffffff PARAMETER C_MEM1_BASEADDR = 0xe0000000 PARAMETER C_MEM1_HIGHADDR = 0xefffffff BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0 PORT Clk90_in = clk_90_s PORT Clk90_in_n = clk_90_n_s PORT PLB_Clk_n = sys_clk_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s END

Paul Lee wrote:

thanks for the info.

Cheers Paul

Eli Hughes wrote: