Field-Programmable Gate Arrays

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3 comments posted 20yrs

posted by tony

3 comments posted 20yrs posted by tony

ISE 8.1 Comment Bug, Very hideous

The following code was shown to me by a collegue. All of the logic has been removed for clarity (and to protect IP). Th...

11 comments posted 20yrs

posted by emh203

11 comments posted 20yrs posted by emh203

Output bus bit resolution of a digital filter

Hello all, Does anyone know of a link/web page/article/ that gives the equations to calculating the output databus bit...

1 comments posted 20yrs

posted by rover8898

1 comments posted 20yrs posted by rover8898

ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'

hi everyone, i am curently debugging a board developed havin vitex chip... when i try to program this board following e...

2 comments posted 20yrs

posted by aborundiya

2 comments posted 20yrs posted by aborundiya

Question about the ip I developed

Hallo, I'm working as hardware developer into an industry. I began one year ago. I have recently received a job offer f...

9 comments posted 20yrs

posted by marc

9 comments posted 20yrs posted by marc

Where has the ChipViewer gone

Hi, I'm using ISE 8.1.02, and when working with a 9500XL device I cannot see the Chip Viewer -- other users have posted...

0 comments posted 20yrs

posted by gavin.melville

0 comments posted 20yrs posted by gavin.melville

fpga programming

hi all! what hapens when i send a code written in vhdl through jtag to the fpga? if anyone can tell me in detail the pro...

3 comments posted 20yrs

posted by ashutoshkaushik

3 comments posted 20yrs posted by ashutoshkaushik

Microblaze GPIO (basic) question

Dear All, For my application, I'm using a Spartan-3 Starter Kit Board, with a microblaze microcontroller (uart, timer,...

1 comments posted 20yrs

posted by jmariano

1 comments posted 20yrs posted by jmariano

OPB Clocking Question

I am working with an embedded MicroBlaze project that has multiple Xilinx cores and multiple custom IP cores. The FPGA...

1 comments posted 20yrs

posted by mottoblatto

1 comments posted 20yrs posted by mottoblatto

design optimization

Hi, I am targeting the design for XC2C512 coolrunner device. That's the biggest device i could find. Are you aware of a...

12 comments posted 20yrs

posted by harikris

12 comments posted 20yrs posted by harikris

Xilinx MPPR failing

Hi all, I have a problem with MPPR (MultiPass Place and Route). The first pass ends normally but at the begin of the pl...

0 comments posted 20yrs

posted by taileb.mehdi

0 comments posted 20yrs posted by taileb.mehdi

ML403 ZBT SRAM

Hi all, I'm trying to develop a controller for the ZBT SRAM present on the ML403 board. When I make a post P&R simulati...

4 comments posted 20yrs

posted by taileb.mehdi

4 comments posted 20yrs posted by taileb.mehdi

Xilinx PROM

I may have overlooked something but I cant seem to find the dimensions o the platform flash PROM in a FS48 package. I h...

3 comments posted 20yrs

posted by maxascent

3 comments posted 20yrs posted by maxascent

FPGA Single LED Demos: FPGA board for a good ideas/suggestions

Hi all I am looking for ideas for: "FPGA Single LED Demos", The requirements for the demo Application are following: *...

26 comments posted 20yrs

posted by antti

26 comments posted 20yrs posted by antti

Reset

Hi, What is the difference between Asynchronous and Synchronous reset. When do you want to use one of them. I am desgin...

4 comments posted 20yrs

posted by fpgalearner

4 comments posted 20yrs posted by fpgalearner