ISE 8.1 Comment Bug, Very hideous

Oops, here is the verilog code:

module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 , COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo);

/*inputs outputs registers wires*/ input SysReset; output Zero; input ClkInput; input UZBEERX; output [12:0] ROW_Q1; // row select quadrant1 output [12:0] COL_Q1; // column select quadrant1 output [12:0] ROW_Q2; // row select quadrant2 output [12:0] COL_Q2; // column select quadrant2 output [12:0] ROW_Q3; // row select quadrant3 output [12:0] COL_Q3; // column select quadrant3 output [12:0] ROW_Q4; // row select quadrant4 output [12:0] COL_Q4; // column select quadrant4 output [3:0] PSUP; output [3:0] PSUPo; endmodule

some long time ago writing your company name in non-ascii chars like a-umlaut a" in the schematic template header of the Xilinx ECS rendered the schematic to invalid, so you lost your work (ok it was possible to use binary editor to fix the char)

- the comment type of error in Xilinx ISE/XST means that Xilinx is not using a proper qualified VHDL/verilog parser - a proper parser would not chokes on comments (in places where those are legal as per language reference)

Antti

Eli-

This happens in 7.1 also. A couple of years ago a Xilinx FAE told us "do not use C++ style comments for any reason except synthesis attributes" and we have followed that on blind faith.

-Jeff

So, if I cant use // or /* */, what can I use for commenting?

-Eli

Wow, that's a pretty impressive impact/laziness ratio ::

(User Impact x N users) / (Suppliers Time to Fix)

How long _should_ it take to fix this ?

-jg

FWIW the following code seems to work with ise 8.1.03:

module test (test_in1, test_in2, test_out1, test_out2);

input test_in1; // comment here input test_in2; /* comment here */

output /* comment here */ test_out1; output test_out2; /* comment here and here */

assign test_out1 = test_in1; assign test_out2 = test_in2;

endmodule // test

HTH, Jim

Quick question: why aren't you using the modern ANSI-C-style declarations?

-a

Eli-

By "line comments" I thought you meant C++ style comments. I've not had trouble with /* ... */ in 7.1, only with //. My apologies for answer that was not helpful.

-Jeff

I am the collegue Eli spoke of. I did not have problems with 7.1, only

8.1. I have also noticed that pushing the enter button does not go to the next line until I start typing after pressing enter. Also, after a // comment, if I press enter, the next line actually turns green. I had to delete and press enter a few times to get it to not show up green like a comment, but the synthesiser still recognizes it as one, as seen in Eli's example.

-Jon

Hi Everyone,

Can someone open a Tech Support case on this issue? It has nothing to do with the fact XST does not support the comment style. This has always worked. The problem is that you are using reserved words in verilog. There is a fine distinguising part here as well. XST needs to read through the comments to get the synthesis attribute keywords. There sounds to be a bug where we are only looking at keywords and not looking for the synthesis attribute statement.

This is a bug and the reason why it worked in 7.1i and not in 8.1i is because this capability was moved from the engine to the parser and the parser somehow missed out on this check. Thus it looks like ISE 8.1i broke something.

There should be a way to work around this too. Try the following change to your comment:

From:

/*inputs outputs registers wires*/

To:

/*This section declares the inputs outputs registers wires for the module*/

Either way it is a bug and so go ahead and open a Xilinx Tech Support case on it.

Thanks Duth

snipped-for-privacy@gmail.com wrote:

Could there be more than one issue here ? Someone said it also fails in v7.1i, and to avoid //,

- your example is slightly different, showing a parser/keyword-in-comnent problem ?

-jg

Duth wrote: