Field-Programmable Gate Arrays

Book Software for XC3190A?

Hi, is it possible to program the XC3190A with the tools in the book: The Practical Xilinx Designer Lab Book: Version 1....

15 comments posted 20yrs

posted by tuxfriend

15 comments posted 20yrs posted by tuxfriend

Quartus and source control

Hello all, I'm interested in implementing a source control system (Subversion) in the company I work. We do mostly Alte...

28 comments posted 20yrs

posted by avishorp

28 comments posted 20yrs posted by avishorp

URGENT: Xilinx site

Hi all, Is the Xilinx's site working ok? for me almost all the links are not working!! Thanks in advance for quick reply

5 comments posted 20yrs

posted by taileb.mehdi

5 comments posted 20yrs posted by taileb.mehdi

How to see *.vcd file outported from ChipScope from different computer

Hi, I am the first time user of Xilinx ChipScope. Now the waveform file *.vcd outported from Xilinx ChipScope is in lab...

3 comments posted 20yrs

posted by wtxwtx

3 comments posted 20yrs posted by wtxwtx

PCI bridge

Hi, does anyone use Opencores PCI bridge with Altera devices ? My card works fine with Altera core, but i want to imple...

0 comments posted 20yrs

posted by grzegorz.swiecanski

0 comments posted 20yrs posted by grzegorz.swiecanski

DRC has announced its newest FPGA that drops into AMD's Socket 940

http://www.dailytech.com/article.aspx?newsid=1920 So... I do see a possibility here.

12 comments posted 20yrs

posted by pNaonStpealmtje

12 comments posted 20yrs posted by pNaonStpealmtje

Pull up resistors on Spartan 3 mode pins

People here are driving me crazy insisting that the Xilinx factory has told them that you *MUST* tie the mode pins to e...

29 comments posted 20yrs

posted by spamgoeshere4

29 comments posted 20yrs posted by spamgoeshere4

please help me out

hey friends , I'm trying to design an interface between a ps2 keyboard and the digilent DIO5 board which contains a Xil...

1 comments posted 20yrs

posted by aldalbahi

1 comments posted 20yrs posted by aldalbahi

Opteron HT coprocessors

In comp.arch (and others) there is a thread on this Opteron Virtex4 coprocessor that sits in socket 940. http://www.dai...

12 comments posted 20yrs

posted by johnjakson

12 comments posted 20yrs posted by johnjakson

What would be the tariff classification of an FPGA development board?

I was wondering what's the tariff classification of an FPGA development board. Searching through some documentations, I...

5 comments posted 20yrs

posted by jaxato

5 comments posted 20yrs posted by jaxato

help me friend

Respected , knowledgious people,i m student of M.Sc. Electronics 4th semister .i m working on a project on newer tech....

2 comments posted 20yrs

posted by kapilaryan2003

2 comments posted 20yrs posted by kapilaryan2003

Xilinix SPI programming with USB Platform Cable

So I want to program a serial data flash (SDF) using the SPI protocol but my board/software seems to be unhappy with th...

5 comments posted 20yrs

posted by andrew.hood

5 comments posted 20yrs posted by andrew.hood

Bus macros compatible with ISE 8.1

Hello, Could someone please send me a tri-state bus macro for spartan2 ? Thanks in advance, Fabio

0 comments posted 20yrs

posted by fabio.rocha

0 comments posted 20yrs posted by fabio.rocha

HSTL classes and termination schemes

JEDEC defines various classes and termination schemes for HSTL: I unterminated or symmetrically single parallel II sour...

2 comments posted 20yrs

posted by rreuter

2 comments posted 20yrs posted by rreuter

Assigning MGT's in sample Aurora Design

Hi There, I just generated a Aurora sample design that communicates between 2 MGT's using Coregenerator. How do I confi...

4 comments posted 20yrs

posted by bkamakot

4 comments posted 20yrs posted by bkamakot