design optimization

How can we possibly help you, when we know nothing about your design? Peter Alfke

Aren't you and Xilinx developing a new line of FPGA's called "The Crystal Ball Series"? Parallel psychic processing that transcends the sphere of phsyical science or knowledge.

Sorry, I couldn't resist.

schrieb im Newsbeitrag news: snipped-for-privacy@v46g2000cwv.googlegroups.com...

there are almost no generic rules, but specially for PLDs the design for PLD optimization can yield in huge macrocell reduction.

if your current count is 524, then I would say with 99.9% that the desing can be made fit into 512 unless you have already spent over one man-month in PLD specific optimization to get the MC count down to 524.

the easiest way to find some resources is to find some block that are never active at same time and use 1 extra MC to flag for resource sharing

as example if you need counter and shift register but not at the same time then almost all MCs uses in counter and shift register could be shared.

besides that there are pretty many things for PLD that can influence the design fit, but again no golden rule for you, its all design specific and based on general 'it doesnt fit' there is little help that could be given to you

Antti

Rob schrieb:

How dare you write this in a newsgroup? I had to sign an NDA on that topic.

Kolja Sulimma

"Kolja Sulimma" schrieb im Newsbeitrag news:44550796$0$4514$ snipped-for-privacy@newsread2.arcor-online.net...

is there an April joke somewhere? 'Crystal Ball' !?

Antti

There are plenty : Lattice MachXO, Altera MAX II are the 'new designs' arena, Lattice & Actel also have FLASH FPGAs, and lattice have older CPLD families that are > 512 MCells, but their price/ability point is probably not ideal these days.

See other threads, on how to create Dual Edge using two single edge FF+XOR. Plus, you can always clock double, or use a PLL.

Scan thru the FIT RPT file, and look at your modules, for resource usage. Sometime it is easier to compile portions of the design, and paste those summaries, then scan them with your eye and a pencil, for ones that use more that their 'fair share' of resource. A small change in HDL coding can give a big change in resource.

-jg

Hi Lukats/Jim,

Thanks for the sugggestions. I will work on those lines. I have not spent nearly a day thus far to try fit the design and your comments seem to be encouraging.

Thanks.

You can try turning on the ISE options optimize density, and exhaustive fit. The result is a design that uses fewer gates, etc, but runs slower. If you accidentally created latches, they will eat up chip resources.

-Dave Pollum

So *that* is what that recent Xilinx patent on LUTs with negative 100 ps propogation delay is all about. Daisy-chain enough of those, and you could really do some amazing things!

Given how exotic the materials needed to fabricate these parts are, I expect that they will be priced too high for my budget.

Eric

The problem is that they only work until you program them.

However, since software and firmware are usually very late, that means that you can deliver when marketing has promised your product, and it will be out of warantee by the time you deliver the code and it stops working.

As someone has gone and blabbed this into a public newsgroup, I can reveal that Googling for "The Endochronic Properties of Resublimated Thiotimoline" will reveal more about the materials used. HTH, Syms.

that they

The rumors must be true. I asked my local distributor and they have not listed these parts. Drawing from Spartan-2 and Spartan-3 experience this is a sure sign that millions of pieces have been sold allready.

Kolja Sulimma