Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

initial block processing in XST 8.1

All- I recently opened a case with Xilinx about initializing arrays of registers (search for thread "initializing array...
2 comments posted 20yrs
posted by jbrower
2 comments posted 20yrs posted by jbrower

ispLEVER Starter 6.0 FPGA Design Software Available

Lattice has released a new version of our downloadable ispLEVER Starter software, concurrent with version 6.0. Device s...
12 comments posted 20yrs
posted by bart.borosky
12 comments posted 20yrs posted by bart.borosky

xilinx V4 obufds_25 and 3.3 V

Hi All, Let say I have one bank in V4 device with all single ended outputs and one differential output. I'd like to hav...
3 comments posted 20yrs
posted by
3 comments posted 20yrs posted by

PLB clocking

Hi, I have a cutom IP that i want to run at lest say at 80 Hz. I want to atatch this IP to PLB Bus which has clock runn...
2 comments posted 20yrs
posted by fpgalearner
2 comments posted 20yrs posted by fpgalearner

Xilinx/Synplicity LUT Placement

Folks, Does anyone know if either Xilinx or Synplicity have provided a mechanism to explicitly place an inferred LUT? I...
4 comments posted 20yrs
posted by johnhandwork
4 comments posted 20yrs posted by johnhandwork

[Newbie] Suitable FPGA for my project

Hi all. I'm a total newbie to FPGA programming, therefore I'm looking for suggestions. In my project I have the followi...
8 comments posted 20yrs
posted by trapule
8 comments posted 20yrs posted by trapule

CPLD (CoolRunner) failures.

has anyone experienced problems when operating Cool Runner (XPLA3) CPLDs near the capacity of their macrocells? specifi...
2 comments posted 20yrs
posted by neilchamberlain
2 comments posted 20yrs posted by neilchamberlain

Xilinx-ise, invert input?

How does one modify say a 'fdcp' block/object such that PRE & CLR is inverted..? without resorting to adding external in...
3 comments posted 20yrs
posted by pbdelete
3 comments posted 20yrs posted by pbdelete

Use USB ports on ML401

Hi everybody! I would like to use the USB host and peripheral ports on my ML401 development board but I don't know what...
2 comments posted 20yrs
posted by max.giacometti
2 comments posted 20yrs posted by max.giacometti

LISP Workshop at ECOOP06

Hi, on the upcoming ECOOP conference in Nantes, France, the 3rd European LISP Workshop will be held. Part of that works...
7 comments posted 20yrs
posted by hans.huebner
7 comments posted 20yrs posted by hans.huebner

Ethernet & ML401

Hi everybody! I would like to use the ethernet port on my ML401 development board (equipped with a Xilinx Virtex4 FPGA...
8 comments posted 20yrs
posted by max.giacometti
8 comments posted 20yrs posted by max.giacometti

Memory Interface: Standards

Hi, I'm a beginner to Verilog. Is there any standardized or "typical" Application Interface Layer for accessing general...
0 comments posted 20yrs
posted by nobody
0 comments posted 20yrs posted by nobody

generate a square signal with a 3.8 ns "plate"

Hi, I want to generate this kind of signal with my spartan 3 XCS200 : http://www.abcelectronique.com/forum/attachment.p...
8 comments posted 20yrs
posted by romaingoron
8 comments posted 20yrs posted by romaingoron

EDK OPB DDR2 IP Core, looking for tested example

Hi while looking for help at Xilinx website I found already application notes about the DDR2 and Virtex5, but I am stil...
1 comments posted 20yrs
posted by Antti.Lukats
1 comments posted 20yrs posted by Antti.Lukats