Lattice has released a new version of our downloadable ispLEVER Starter software, concurrent with version 6.0. Device support includes the 90nm LatticeECP2-50 and can be downloaded here:
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Regards, Bart Borosky, Lattice
ispLEVER Starter 6.0 FPGA Design Software Available
May 20, 2006
12 Replies
"bart" schrieb im Newsbeitrag news: snipped-for-privacy@j73g2000cwa.googlegroups.com...
are XP devices now suported in schematic?
antti
Native Fedora/Debian linux versions?
Still without even the simplest free simulator?
Best regards Piotr Wyderski
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Piotr, In my opinion, if your design needs a simulator, then you better spend some money on a real good simulator. BTW, the full version of ispLEVER has ModelSim as simulator and the list price on Lattice's website is $695, and when you order online 'only' $495. For this price you get the OEM version of ModelSim - and this is by far the best deal you can get
Regards, Luc
Any idea what the limitations of the OEM version of Modelsim are for the Lattice OEM version?
John Providenza
John,
No X-Tracer
25-30% slower as full version (Altera has same limitation, Xilinx has even slower version)That's it.
Luc
Every design needs a simulator. Even as simple as that one from Quartus Webpack -- it is still infinitely better than no simulator.
Currently the best deal I can get is not to use Lattice or Actel parts -- the other vendors provide all the necessary tools.
Best regards Piotr Wyderski
I use xilinx build in simulator for Lattice designs :) or ok usually I am not doing that either.
but sure a simulator is a nice a have feature (when it is available)
Antti
Luc -
The last version of ModelSim/Altera that I purchased had a limitation of the number of instantiations you were allowed. If I started manually instantiating IO buffers for wide ram busses, I'd hit the limit and ModelSim would refuse to run.
John Providenza
John,
There is indeed a 255-instance limit, so that is correct. However, as you can see from being able to run gate-level simulations, this limitation is not there when actually instantiating Altera cell primitives.
Thus, I'm not entirely sure how you ran into this limit, unless you wrapped the BIDIRs into something slightly higher-level.
BTW: Why did you instantiate those IO buffers? So far I've always been able to infer them.
Best regards,
Ben
Piotr Wyderski wrote: > Still without even the simplest free simulator?
I use the free Icarus Simulator at:
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and I think it's great. Although it doesn't have a GUI interface, it's very simple and easy to use. I even use it in preference to the free simulators offered by some of the FPGA vendors, and have used it to develop a 2,000+ line Verilog program to implement the Elliptic Curve Factoring method an FPGA.
Ron
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