Does anyone know if either Xilinx or Synplicity have provided a mechanism to explicitly place an inferred LUT?
I can produce LUTs that only feed a keep_buf but don't maintain the same LUT name across compiles for RLOCing. I can guarantee the net name for Place & route with the keep_buf but can't associate the net with the LUT's placement.
I'd love for the Xilinx tools to propagate a location constraint back to the primitive that drives it since Synplicity hasn't come up with a nice way to guarantee a net driver's name.
Any help is appreciated,