Xilinx-ise, invert input?

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How does one modify say a 'fdcp' block/object such that PRE & CLR
is inverted..?  without resorting to adding external inverters.

Re: Xilinx-ise, invert input?
noway, its not Altera SW!

Re: Xilinx-ise, invert input?
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So if I want an asynchronous flip-flip with D, Q, _Q, CLK, _PRE, _CLR as one
"symbol" in schmatic. How do I accomplish this ?

Re: Xilinx-ise, invert input?
write VHDL wrapper around the components, implement there inversion and
convert to schematic symbol


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