How does one modify say a 'fdcp' block/object such that PRE & CLR is inverted..? without resorting to adding external inverters.
Xilinx-ise, invert input?
May 19, 2006
3 Replies
noway, its not Altera SW!
So if I want an asynchronous flip-flip with D, Q, _Q, CLK, _PRE, _CLR as one "symbol" in schmatic. How do I accomplish this ?
write VHDL wrapper around the components, implement there inversion and convert to schematic symbol
antti
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