Memory Interface: Standards

Hi,

I'm a beginner to Verilog.

Is there any standardized or "typical" Application Interface Layer for accessing general memory in Verilog?

I found a document showing an example of how to access Block Select RAM in Spartan II.

I also found an internet page showing a small example (www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.8.htm)

Both examples end up in something like module MYMEM(CLK, WE, ADDR, DIN, DOUT)

My question is; is this the accepted common way of accessing general memory? Are there any good links or references for this subject?

Thanks DeMarcus