xilinx V4 obufds_25 and 3.3 V

May 19, 2006 3 Replies
L

Hi All,



Let say I have one bank in V4 device with all single ended outputs and one differential output. I'd like to have VCCO =3.3V.



This is not allowed in V4, because obufds_33 doesn't exist in V4 and PAR ends with error.



What going to happen if I'll declare all outputs in this bank as LVCMOS_25 and LVDS_25, but physically connect VCCO to 3.3V on board?



Will it damage the device?



Probably I'll get some out-of-spec voltage levels for LVDS output. But it's fine for me.



My situation is that diff output CLK signal was overlooked on the board and placed in the 3.3V bank. Board can work with single ended CLK signal but it's better to have differential.



Thanks


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A

schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...

should be ok, even if not spc

antti

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L

Thanks Antti, It's interesting why xilinx doesn't show this as a solution. If it doesn't hurt, I'd prefer that tools allow me to use obufds_33, even it is slightly out of spec. I suppose even input LVCMOS_25 under 3.3 V will work fine in most applications.

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A

well Xilinx cant put into datasheet what is out of spec.

Antti

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