Field-Programmable Gate Arrays

Spartan 3e sample: pack power control with M(1)?

Guys/Gals, I was lucky enough to score a Digilent Spartan 3e sample pack board. This board is interesting in that it ca...

2 comments posted 20yrs

posted by jshamlet

2 comments posted 20yrs posted by jshamlet

Processing DVI signals with an FPGA

A friend and I have come up with some interesting ideas that involve messing around with DVI interfaces, and we'd like...

2 comments posted 20yrs

posted by patches11

2 comments posted 20yrs posted by patches11

V5 and carry lookahead

I was axcited when I read "carry lookahead" with respect to V5. But when looking at the diagrams in the user guide it l...

7 comments posted 20yrs

posted by acd4usenet

7 comments posted 20yrs posted by acd4usenet

DCM and Clock

Hi, Considering me a newcommer to FPGA world. I am trying to use Virtex 4FX series for a synchronous design, meaning i...

11 comments posted 20yrs

posted by fpgalearner

11 comments posted 20yrs posted by fpgalearner

Output gain adjuster of digital filters

Hello all, I recently learned/heard that when implementing a IIR digital filter of direct form I, the gain has to be fi...

5 comments posted 20yrs

posted by rover8898

5 comments posted 20yrs posted by rover8898

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0 comments posted 20yrs

posted by sgblookatme22

0 comments posted 20yrs posted by sgblookatme22

Spartan 3 Readback

I am working on a custom configuration controller that configures a Spartan 3 through SelectMap and verifies the config...

8 comments posted 20yrs

posted by johannes.vanderhorst

8 comments posted 20yrs posted by johannes.vanderhorst

FPGA Configuration Question

This is a very simple question, but is something that I have taken for granted with all of the nice tools. For the Xili...

4 comments posted 20yrs

posted by emh203

4 comments posted 20yrs posted by emh203

OFFSET constraints with derived clocks - Xilinx FPGA

Hello, I am using Virtex2p Xilinx FPGA. My design accepts a clock input of 25Mzh. A system clock of 75Mhz is derived fr...

1 comments posted 20yrs

posted by muthusnv

1 comments posted 20yrs posted by muthusnv

FPGA and Reconfigurable Programming Glossary

Dear All, As part of our project of making a multi-discipline glossary in our site http://www.webservicesfree.com you ar...

2 comments posted 20yrs

posted by smart_outsourcing

2 comments posted 20yrs posted by smart_outsourcing

Clocking ZBT RAM via DCM on ML40x board

Hello, I'm trying to use a DCM to deskew the memory clock but find it hard to learn which pads should be used to create...

3 comments posted 20yrs

posted by tomdz

3 comments posted 20yrs posted by tomdz

Where can i get "Quartus II Device Information for UNIX & Linux CD"

Hi, I am tring to install Altera Quartus II v6.0 under Debian 3.1. During the install process, the install script ask m...

2 comments posted 20yrs

posted by huymEmail

2 comments posted 20yrs posted by huymEmail

Update: Simple ADS5273 -> Xilinx Interconnect Model

Following up on an older thread: http://www.fpga-faq.org/archives/97450.html#97451 http://groups.google.com/group/comp....

0 comments posted 20yrs

posted by brimdavis

0 comments posted 20yrs posted by brimdavis

V4 system synchronous input setup/hold and clock-to-out time calculations?

Greetings, I want to know the input setup/hold and clock-to-out times for LVCMOS18 fast 16mA for an LX40-10 part, and I...

0 comments posted 20yrs

posted by nimby1_NEEDSPAM

0 comments posted 20yrs posted by nimby1_NEEDSPAM

Verilog Draggable Window Library

HWGUI is a Verilog library which generates windows with captions on a VGA display. This uses no microprocessors; a stat...

1 comments posted 20yrs

posted by tbfleming

1 comments posted 20yrs posted by tbfleming