I want to constrain the max fanout for a particular net in my design. I am using the XPS flow and the net I want to constrain is a BRAM address signal and is generate by xps, during platgen I suppose. I don't think I can just go in and add attribute constraints to the system.vhd file in the hdl/ directory because those files seem to be regenerate every time. How can I constrain the fanout for this net? Thanks for any pointers.
Matt
An update if anyone was interested: I tried to constrain the net in the system.vhd file as stated below. These constraints were noted by the synthesizer but for some reason the fanout is as before, according to the timing analyzer. Any thoughts?
Matt
Matt Blant> I want to constrain the max fanout for a particular net in my design. I am
Matt, why do you think that you need to constrain the fan-out? Do you have an indication that delays are excessive? Peter Alfke, Xilinx
Peter,
Yes, the fanout is excessive. I have a fanout of 32. With 0 logic levels, the delay from that net exceeds my required period. I am hoping that reducing the fanout will reduce the delay from that net.
Matt
Peter Alfke wrote:
What device, and what delay at fanout=32? Peter Alfke
I'm using an xc2vp70-ff1704-7. The delay from the net is 4.052 ns, the total delay is 4.692 ns.
Matt
Peter Alfke wrote:
A fanout of 32 shouldn't be excessive. You would probably benefit from a little floorplanning. If you constrain this logic to a small area, the routing delays will decrease. Look for 'area group' in the constraints guide
-- Joe Samson Pixel Velocity
Unfortunately this signal is going to several modules which are in different parts of the chip. Thanks for the suggestion though.
Matt
Joseph Sams> Matt Blant>> I'm using an xc2vp70-ff1704-7. The delay from the net is 4.052 ns, the
I managed to get around the issue by manually inserting copies of the register containing the signal with the high fanout. This solves my initial problem but unfortunately doesn't explain why setting the max fanout wasn't working. Thanks to all that replied.
Matt
Matt Blant> I want to constrain the max fanout for a particular net in my design. I am
When flipflops get replicated by synthesis to reduce fanout, they get named by the tool in such a way as to make the mapper think they are part of a bus and then they get put in the same slice, never-more to be separated. This happens because they have anumber on the end of the original name.
If you replicate by hand and name them _a, _b, etc this problem doesn't happen.
Apprarantly even XST get's it wrong, and it should know better!
Cheers, Martin
-- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conekt
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