Field-Programmable Gate Arrays

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MachXO primary clock example (PCLK)

Hi! I'd like to use an external 25MHz TCXO as a primary clock. Unfortunately, t he application notes (at least what I'v...
0 comments posted 12yrs
posted by gergo.santha
0 comments posted 12yrs posted by gergo.santha

22V10 programmer

Does anyone know of a cheap 22V10 programmer ? or maybe a Atmel ATFxxxx programmer ?
16 comments posted 12yrs
posted by hamilton
16 comments posted 12yrs posted by hamilton

HELP: Edge triggering of mode register, Verilog

I'm a relative Verilog noob, and stuck on the following, not sure if I'm structuring the problem wrongly or if it's jus...
6 comments posted 12yrs
posted by Bruce Varley
6 comments posted 12yrs posted by Bruce Varley

Access custom VHDL types in TCL script

Hi Guys, I'm having a custom type in VHDL: type alu_op_code is ( ALU_OP_IDLE, ... ); Now having a testbench written in...
3 comments posted 12yrs
posted by rschilling
3 comments posted 12yrs posted by rschilling

Ethernet Switch on Configurable Logic now available

Now available from our Opencores.org repository a highly configurable Ethernet Switch for FPGA implementations. Check ht...
0 comments posted 12yrs
posted by spamaarsen
0 comments posted 12yrs posted by spamaarsen

Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr....
0 comments posted 12yrs
posted by sim2a2z
0 comments posted 12yrs posted by sim2a2z

ECG signals Compression/Decompression

Hi, I want to ask you if it's feasible to create an ECG compression/decompression algorithm using decomposition of the...
29 comments posted 12yrs
posted by 100383
29 comments posted 12yrs posted by 100383

shift register (invariable size) FIFO = ?

Hi, if I chain up a bunch or registers (or use shift registers), the data comes out only after it has passed through th...
2 comments posted 12yrs
posted by 24789
2 comments posted 12yrs posted by 24789

Trigger implementation on ADC-FPGA

Hi, I'm trying to implement hardware trigger functionality by modifying the FPG A code for the LM97600RB from Texas Ins...
8 comments posted 12yrs
posted by syed.huq.a
8 comments posted 12yrs posted by syed.huq.a

FSL Bus Problem

Hi everybody, I have connected a coprocessor to Microblaze in EDK through FSL. My problem is when i read data from FSL...
0 comments posted 12yrs
posted by manou.makni
0 comments posted 12yrs posted by manou.makni

integrate microblaze in ISE and VHDL code

Dear all, I'm beginner to use microblaze. I made a simple program to read two numbers from uart and add them using micr...
0 comments posted 12yrs
posted by 100283
0 comments posted 12yrs posted by 100283

Re: Microblaze and MBLite

[] >>My goal is to connect >>the MBLite opencore processor to the Xilinx Microblaze. The problem is that >>MBLite suppo...
5 comments posted 12yrs
posted by al.basili
5 comments posted 12yrs posted by al.basili

Signal Integrity Failure on Custom FPGA board

Hi I have just gotten a custom FPGA board in house and I am having trouble programming it. The FPGA I am using the Acte...
3 comments posted 12yrs
posted by 100254
3 comments posted 12yrs posted by 100254