Latest threads in Field-Programmable Gate Arrays

Undriven outputs of a module in Quartus II Synthesis

I have a module which does not drive certain output ports for certain operation modes, and that simulates fine in Model...

9 12yrs

angzhiping

9 12yrs angzhiping

virtex4 software reset problem.

HI I made a small amendment to a tutorial I found online "http://www.fpgadeveloper.com/2008/02/integrating-vhdl-design-...

0 12yrs

khan990

0 12yrs khan990

need coding

TITLE Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES Design and development of CCSDS based Telemetr...

26 12yrs

saqi0313saqi

26 12yrs saqi0313saqi

Call for Papers :: ICETC2014 :: Poland

The International Conference on Education Technologies and Computers (ICETC 2014) September 22-24, 2014 Lodz University...

0 12yrs

sdiwc.org

0 12yrs sdiwc.org

in my xps implementaion elf file is not generated only the linker script is generated

these are my errors /cygdrive/c/Xilinx/12.1/ISE_DS/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../...

1 12yrs

grg.levi

1 12yrs grg.levi

The USB FPGA?

I've been pondering... When it comes to attaching an FPGA to a PC, there are lots of options. First there's JTAG, then...

16 12yrs

theom+news

16 12yrs theom+news

Free alternatives to Xilinx iMPACT?

I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to program CPLDs. Is there a free alternative (prefe...

6 12yrs

pkk

6 12yrs pkk

Old Spartan-II demo board from Insight - seeking docs.. (2026 Update)

I have dug out an old board with Spartan-II XC2S100 chip and I could use it, if only I could get some documentation for...

6 12yrs

brankob

6 12yrs brankob

Lattice MICO32 won't generate?

Hi, I downloaded Lattice's MICO system for windows. It opens up Eclipse, where I can add processor and memory, make bus...

1 12yrs

24789

1 12yrs 24789

Synthesis / PAR options mess up design functionality

Hi, I'm running into a problem with a memory controller design (mid-range FPGA, 76% utilization) and am wondering if an...

3 12yrs

harnhua

3 12yrs harnhua

Ethernet interfacing

Any one did ethernet interfacing in Xilinx Vertex 5.

2 12yrs

akshayeldhojose

2 12yrs akshayeldhojose

unclear tcl error

Hi everyone, I must admit that I'm pretty new to tcl scripting so this error might be plain stupid but I've failed to u...

2 12yrs

al.basili

2 12yrs al.basili

JTAG issues Cyclone V SoC

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module th...

3 12yrs

aclark

3 12yrs aclark

Recovering verilog source file from build files.. possible?

My .v Verilog source files were in a separate folder to the IDE build directory, containing all the stuff generated in...

0 12yrs

nospam

0 12yrs nospam

Cheap spec an using an RTL-SDR

http://hansvi.be/wordpress/?p=91

0 12yrs

lcargill99

0 12yrs lcargill99

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