shift register (invariable size) FIFO = ?

Question

Hi,

if I chain up a bunch or registers (or use shift registers), the data comes out only after it has passed through the whole memory length. Even though "first in" comes out first, at least [1] states on page 2 that this is usually not referred to as "a" FIFO . On the other hand, a "conventional" memory-based FIFO gives the output more or less immediately, as it has variable size.

My question is, do those two types of memories have commonly accepted names to distinguish between them, for example when commenting code? I was about to call the "invariable size" variant a "pipe", but maybe there is a better term?

[1]

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Richard Damon · Accepted Answer

A block where the data comes out N cycles after it goes in is generally (at least in my experience) called a pipeline, delay line, or shift register.

The key difference between this sort of module and a FIFO, is that a FIFO generally runs "intermittently", where at least one (but normally both) of the input or the output only transfers data on some control signal.

A Pipeline tends to always run, though sometimes there is a "Hold" signal that stops the shifting.

mnentwig · Answer

Thanks! "Delay line" it shall be then. 	    					 ---------------------------------------		 Posted through

shift register (invariable size) FIFO = ?

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