Hi,
I'm trying to implement hardware trigger functionality by modifying the FPG A code for the LM97600RB from Texas Instruments which uses a Virtex-5 FPGA, and then implementing it on our custom board but I had a few questions wit h regards to it.
From what I understand of how the trigger works, the data keeps being captu red continuously by the ADC, but the trigger functionality would only kick in when the data is being stored. Am I right in that assumption? Maybe I ne ed to keep checking the trigger and only when the board is triggered, I all ow the data to be stored inside the internal RAM of the FPGA? Or is there a n alternate way to do this? I'm currently storing the data samples using th e Block RAM of the FPGA.
If my thinking is right, when the the board is triggered, and the data star ts being captured, I lose a few data samples due to the delay in the trigge r registering and then the data being stored. How do I overcome this? Even a few nanoseconds of data is important in this case.
I'd appreciate any ideas on this. Thanks!