HELP: Edge triggering of mode register, Verilog

I'm no expert in Verilog, I'm much more a VHDL guy. When I need to work in it I have to pull out the books to refresh my memory of the syntax, etc or I just pull up my previous code and review it. But I can see what you are doing wrong easily.

Mode is a single variable which can only be assigned in one process... (remember that I'm a VHDL guy so maybe this is wrong). You seem to have three processes. The edge thing is for when you are defining a clocked register, you refer to the edge of the clock. So it would be more like...

always @ (posedge clock) if (Switch = 1) then Mode

Hi,

your approach is typical digital-design textbook but it's completely wrong for an FPGA, sorry.

It will work for a small example but it doesn't scale.

On FPGAs, use synchronous logic. That means, information and the timing is separated. You have information signals and clocks. Edge triggering is done on clocks only.

This matters because clock and information signals are physically separate on the FPGA and you cannot use one in place of the other.

The problem is, generic Verilog tutorials, books etc aren't necessarily applicable to FPGA, because the language is more capable than the hardware. The same for digital design, the FPGA hardware dictates what you can do and (mostly) how it should be done.

Here's how it should look instead: The task is to act on opening or closing switches - detect a transition of the switch signal.

I use a "clk" signal that is available on every FPGA board, let's' say 100 MHz (or whatever)

input wire switch; reg switch_prev = 0; wire switchOn = (switch & !switchPrev); wire switchOff = (!switch && switchPrev); reg pump = 0;

always @(posedge clk) begin if (switchOn) begin pump

Thanks very much, guys,. Your explanations have helped me understand the situation much better.

Hi,

one line was missing:

input wire switch; reg switchPrev = 0; wire switchOn = (switch & !switchPrev); wire switchOff = (!switch && switchPrev); reg pump = 0;

always @(posedge clk) begin switchPrev