other rates. And, by what I know, that occur because the fpga components w hich I'm not using at the design are consuming power.
disabling these components or elaborating better my design.
re if this is the correct way to solve my problem.
It looks like you (or your predecessors, or your boss) had chosen wrong FPG A device. Low dynamic power indicates that device does virtually nothing. So, it almo st certainly was possible to fit your task into much smaller device, e.g. E P2C20 or even EP2C5 instead of big device (what is it, EP2C70 ?) that you a re using now. As to your question, after device was chosen, very little could be done. Th e best you can do is to keep it at the lowest possible temperature - static power consumption strongly depends on the temperature. Also there is a hope that Altera power estimator is to pessimistic.
I assume by now you know that the static power of an FPGA is not a function of your design, but rather of the chip. To lower the static current you need to change chips. Lattice makes the iCE40 devices with static current in the 100 uA range. These are not large parts, but hold a fair amount of logic. They also have a non-volatile configuration storage if needed. Lattice also makes other devices that are low on power consumption although not as low as the iCE40. Check out the XO2 and the XP2 lines.
I am sorry i don't have solution for your problem, but can you please tell me how did you get Power Estimation Confidence High: user provided sufficient toggle rate data in your report, i always get Power Estimation Confidence Low: user provided insufficient toggle rate data in my report, can you tell me how do i provide sufficient toggle rate data.
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