Hi all, I am doing a DDR SDRAM design which is obtained using the MIG tool. The target device is V4LX60. But in that i observed a problem that the controller is using differntial clocking. And IBUFGDP is used to buffer the clcok. The problem is controller needs two differential clcok signals. But the demo board support only one. Tried to assign the same clock to different IBUFGDP units but in the par state it showed an error. Is it possible to assign a differntial clcok signals to two different buffers. Second question is what is the risk involved in changing the RAM controlller code to work with single ended clock. I am planning to use
160 MHz for RAM operation. regards Sumesh V S- posted
17 years ago