Newbie to FPGA

Just to add, I am already comfortable with poking around RTL and large designs, I just havent done the design myself. (Victim of working in a big company :-) )

Are there any more project ideas that will add value to my resume (such as MPEG encoder/decoder etc) that I can do with an FPGA and check out at home using a PC? I have already started designing small modules (fifos etc, mostly synchrounous). Just getting into async fifo design, I still havent understood it fully.

-Anand

anand wrote:

Using a dual-ported RAM, most of any asynchronous FIFO design is trivial. But the devil is in the flags (FULL and EMPTY) which get de-activated by the "wrong" clock. For example: EMPTY is activated by the read clock, and of importance only in that read clock domain, but it gets de-activated by a write clock. There is no defined phase relationship between the two clocks. :-( That clock-domain crossing requires Grray-coded address counters and some trickery to avoid (or mitigate) metastability.

Just google, and read some papers by sunburst or Xilinx/yours truly, like XAPP051.

Peter Alfke, Xilinx

Thanks Peter, I just downloaded XAPP051,

Can you (or someone else) provide some inputs on my post #1 above? Thanks in advance.

-Anand Peter Alfke wrote:

Probably as good as any.

I use Thomas & Moorby's "The Verilog Hardware Description Language", which is mostly about Verilog but sprinkles in guidance for synthesizable designs.

You don't. What's in an FPGA isn't an "application" and it doesn't "run" in the sense that an application does. Once you've _configured_ the FPGA you let it loose, and off it goes doing whatever you coded it to do.

You wouldn't really run a stimulus file through it -- you'd need to use (or generate) an appropriate stream to run in real life to wiggle the inputs pins on your FPGA.

You might want to start out a bit simpler -- I'd suggest blinking the lights, then maybe blinking the lights under the control of the switches.

Thanks Tim. So, if I had to test the application in real life, then I have to stimulate the input pins, correct? So, how do I go about testing on the FPGA as to whether the design actually works in real life (not in simulation)? Assume I have a H.264 stream that I can use.

So in the dev board kit they have flash memory, I guess I can probably load the flash memory with the stimulus stream. But question is, how do I make it wiggle the appropriate pins of the FPGA itself, and how do I collect the output to verify it?

Tim Wescott wrote:

One of the things you can do is to build a stimulus mechanism into your design for both early testing both for simulation and for running in the real chip. Just remember to write it to be synthesisable not testbench style. Once you are confident it is probably working introduce your real source and sort out any issues caused by it being different to your internal stimulus mechanism. For instance dealing with real setup and hold on input signals.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board.

How about a freely available PicoBlaze microcontroller? I assume you can probably write assembly code for the PicoBlaze and that in turn drives the stimulus to the chip.

As for the collection/monitoring of outputs, I believe the Picoblaze can read from the FPGA output pins and either do print statements or populate its own registers for offline reading.

Would this work?

John Adair wrote:

How about a freely available PicoBlaze microcontroller? I assume you can probably write assembly code for the PicoBlaze and that in turn drives the stimulus to the chip.

As for the collection/monitoring of outputs, I believe the Picoblaze can read from the FPGA output pins and either do print statements or populate its own registers for offline reading.

Would this work?

John Adair wrote:

Providing your depth of vectors isn't too large you could do it this way. The standard PicoBlaze has a limited code space and you may need to look at extending it's capabilities by adding on some bits, maybe just a store blockram, if you need a larger depth of vectors. Personally I would be tempted just to use a preloaded blockram with a counter set to wrap around at an appropriate value but that method assumes you have the necessary vectors to start with.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

Wouldn't it also be possible to use the parallel port of a PC to drive the inputs of the FPGA and read back the output signals ? (Of course, some TTL chips might be necessary in addition to that) The PC would also drive the clock of the FPGA in order to "slow down" the circuit.

snipped-for-privacy@gmail.com schrieb:

This is possible but not very usefull. A clean simulation is much easier and much more usefull. So learn it the right way from the beginning on. No need to reinvent the wheel.

Regards Falk