Field-Programmable Gate Arrays

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Bug in Altera Quartus

If you migrate older designs into Quartus you may get some internal errors and the program may crash. I had dug into th...
0 comments posted 20yrs
posted by lecroy7200
0 comments posted 20yrs posted by lecroy7200

Virtex-4 with Rocket IO capability??

Hello, Can anyone suggest a development or evaluation board with Virtex-4 Fpga having rocket IO capability? Thanks, Vive...
5 comments posted 20yrs
posted by vivek.menon79
5 comments posted 20yrs posted by vivek.menon79

ARM cores in FPGA ?

Hi, We have here real good skills in Windows CE software development in our software departement and I was wondering if...
11 comments posted 20yrs
posted by t
11 comments posted 20yrs posted by t

private army of jun g. lockett

all private army and private bodyguard of jun g lockett was killed last night by the tribe of unsaman, and soon the nex...
0 comments posted 20yrs
posted by utahjazz
0 comments posted 20yrs posted by utahjazz

XPLA3 bidirectional bus

Hi all, I implemented a bidirectional bus using tristate buffer inside a XPLA3 device. The CPLD is interconnected to an...
1 comments posted 20yrs
posted by md2003
1 comments posted 20yrs posted by md2003

open inputs and Unisim libraries

Has anyone else seen problems with changes to the latest Xilinx 8.1 Unisim libraries? I loaded up 8.1sp3 to do some S3E...
0 comments posted 20yrs
posted by brimdavis
0 comments posted 20yrs posted by brimdavis

LVTTL or LVCMOS for PCI Signaling?

Is LVTTL or LVCMOS can be used for PCI Signaling? BTW, I'm using Atera MAX-II EPM1270T144C5... - kai -
6 comments posted 20yrs
posted by krbyxtrm
6 comments posted 20yrs posted by krbyxtrm

Xilinx XST Error

At the bottom of this post is the code. First, let me say that I have run this "program" through a TBW, and it seems to...
4 comments posted 20yrs
posted by alexmchale
4 comments posted 20yrs posted by alexmchale

boot mode pins on Spartan3

Hi, on my AD Spartan3 board I have 3 jumpers selecting the boot mode M0-2. They let you connect each pin to GND, so if...
6 comments posted 20yrs
posted by marco
6 comments posted 20yrs posted by marco

ARM9 DDR interface

Hai guys.. I need to setup a V4MB board and interface it with ARM9 core. Is Any one know the good materials or even code...
0 comments posted 20yrs
posted by subin.82
0 comments posted 20yrs posted by subin.82

null waveform element and webpack

Got a quick newbee question. I'm using some source files from the VHDL cookbook which describe a simple CPU. Many of th...
2 comments posted 20yrs
posted by danny.j.voils
2 comments posted 20yrs posted by danny.j.voils

Quartus 6.0 and VCS

Hi, Why is timing simulation with VCS-MX not supported? /michael
0 comments posted 20yrs
posted by michael_laajanen
0 comments posted 20yrs posted by michael_laajanen

S3E Starter Kit webcast

The Xilinx webcast just ended. It was a nice intro to the board; I've got one on my desk so I learned nothing new about...
11 comments posted 20yrs
posted by johnhandwork
11 comments posted 20yrs posted by johnhandwork