bga routing

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I have been doing it last 6 years or so on 1.27 mm pitched BGAs on two signal layers (top and bottom), planes as necessary (actually

6 in all cases so far), 3 lines between BGA pads, pitched 10 mils (say, 5 mils trace and 5 mils gap, these may vary to 4-6 or 6-4). Pad to gap is 5 or even 4 mil, drilling is 0.3mm or 0.2mm (I leave this choice to the PCB house). I drill each BGA pad so I can have access to all signals since my borads are typically expected to begin to work and sell from revision 1; I have posted some info before on how to avoid problems with the drilled BGA pads.

Dimiter

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Marco, try this

Aurash

Marco wrote:

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
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phone:	353 01 4032639
fax:	353 01 4640324

I saw you'r doing radioactive measurement equipment. How do you handle the fpga sensitivity to radiation ..?

I don't. For two reasons - one, because the measuring equipment does not experience any radiation of concern. Often the levels measured are below the natural background, and the detector is placed in a lead shield with 10+ cm walls... There are also high count rate applications, but it is the detector which sees the counts, not the analyzer (several meters cable).

Second, I only use CPLDs, not FPGAs, in my equipment.... :-) :-). (I use Coolrunners).

Dimiter

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pd,

Spartan 3 latest atmospheric neutron readout is 6.3 FIT/Mb. It is still decreasing.

The LANSCE cross sections were less than half V2.

S3 is not recommended for heavy ion applications (space) as there is no mil version with epi wafer.

CERN uses our parts to instrument their beams.

Many labs use our parts.

Unless they are actually near the beam, there is no radiation issue.

If they are near the beam, total dode, and upsets, can be determined, and then mitigated by design.

I leave you with the following: Xilinx FPGAs today allow the engineer to design to, and meet, any arbritrary MTB or FIT rate through the use of various techniques. Doing this some other way is extremely painful, and can not be verified until you are completely finished (when it is too late).

For example, when you think you have a robust design, we have a tool which can go and change individual bits, one by one, or at random. With beam time at more thanb $400 an hour, it is a lot cheaper to verify resiliance to upsets on your bench where you can find it, and then fix it.

Austin

snipped-for-privacy@spamnuke.ludd.luthdelete.se.>>I have been doing it last 6 years or so on 1.27 mm pitched BGAs

Like measureing food activity I guess (or similar tasks). (So you know when you die :)

No RoHS here then :)

Yeah that pretty much solve it I guess. :-) Wonder if actel fpga that uses eeprom cells for config would be at the same radiation level as cpld..

Marco

How many layers you end up using depends a lot on the manufacturer that you use for pcbs and their technology abilities, (principally track and gap and via size etc), that you use. I would say using the FT256 that a

4 layer board is easily viable on the right technology level probably 4/5 thou (0.1-0.127mm) track and gap and maybe down to the easier 6 thou or 0.15mm track and gap. A 6 layer board will probably allow you to use 8 thou or 0.2mm track and gap and allow a wider choice of potential pcb manufacturers. How you do it wil vary a lot depending on your pcb layout and what things connect to and where i.e. where things are placed but to give you a practical example of what can be achieved is our low cost Raggedstone1 product that achieves a full use of XC3S400(264 I/O), in a FG456 package, on a 4 layer board. I will say that wasn't easy even by our standards. The comparitive product of Xilinx(Digilent) Spartan-3E Starter Kit board I believe has 8 layers to do less than we do with I/O.

On a more general point Xilinx used to have breakout patterns for things like Virtex2. Do have a search for those on their site. The is also some useful info here

John Adair Enterpo> Hi all,

Also available at

and the link

Cheers, Philip

Hi,

thank you all for you replies, in my board I have some more bga components like a Blackfin DSP and some memories. I was thinking I'd need at leat 6 layers, including a Vcc plane and a GND plane. Our pcb manufacturer could go down to 4mils tracks and this should allow me to route the board within those 6 layers, but, as long as this is my first bga board, I decided to ask more experinced and skilled people like you how to approach this project (how to start, routing startegies, how many layers and so on).

Marco