Latest threads in Field-Programmable Gate Arrays

minimal connections so that a xcv200e talks with pc

I'm still here,sorry if i post the same message 2 times,but really i'm spending lot of hours daily trying to solve this...

0 20yrs

blisca

0 20yrs blisca

Problem with SLL: "sll can not have such operands in this context" and bit-testing

I've defined this signals: signal accu : std_logic_vector(31 downto 0) := (others => '0'); signal data : integer range...

0 20yrs

fb

0 20yrs fb

Pointers for sending data using ethernet connection from V2Pro

Hi all, I am using a Xilinx V2Pro7 FF672 board. I want to send some data values using an ethernet card.(no Power PC, onl...

4 20yrs

vivek.menon79

4 20yrs vivek.menon79

Missing ISE HTML online help (pdf sucks!)

Is is just me that thinks the pdf documents suck? The html with the docsan search was just awesome! Pdf takes ages to l...

1 20yrs

mleikvol

1 20yrs mleikvol

lwIP on Xilinx Virtex 2 Pro

Hey! I am wondering if anyone has any experience from using lwIP on a Xilinx Virtex 2 Pro and the raw API? I am especial...

0 20yrs

hampus.thorellNOSPAM

0 20yrs hampus.thorellNOSPAM

rocketIO simulation

Does anyone have a feel for at what point rocketIO simulation becomes necessary. I have an FPGA right next to my PCIExp...

1 20yrs

colin_toogood

1 20yrs colin_toogood

Nu Horizon Xilinx 1500 fpga board

Hi, I am a Master student from UNIS and I am doing project about image processing. I am wondering if anyone have a tast...

1 20yrs

eem3kc

1 20yrs eem3kc

property of lockett

the property of jun g. lockett was now owned by unsaman, because jun lockett was surendered to unsaman when his private...

1 20yrs

utahjazz

1 20yrs utahjazz

Help on simulating ddr controler generated by MIG!!

I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct...

1 20yrs

fanhao

1 20yrs fanhao

Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?

I'm considering various options to implement a tapped delay line in an S3 device. I believe that using the carry chain...

3 20yrs

peter

3 20yrs peter

Pc and xcv200e doesn't talk,not exactly the right cable maybe..

I'm still here thanks to this newsgroup i finally built a cable III that works fine with cpld's like xc95144xl(3,3V),i...

4 20yrs

blisca

4 20yrs blisca

How to evaluate the space efficiency of a historic design.

Before I start let me say I'm not sure this is either an intelligent question nor an answerable one... so please be gen...

7 20yrs

pm940

7 20yrs pm940

Altium Designer LiveDesign Evaluation Kits (once again)

Hi all, I know this has been discussed on the NG before, but it seems like every time it is discussed someone hijacks t...

11 20yrs

burn.sir

11 20yrs burn.sir

help downloading picoblaze from xilinx

Hi, I am not able to download the Picoblaze bundle from Xilinx site. The ifulcrum questionnaire crashes on me. Any sugge...

4 20yrs

vivek.menon79

4 20yrs vivek.menon79

RS232 transmitter core--Xilinx xapp223(Chapman's macro)

I came across the Xilinx application xapp223 for the implementation of the UART cores. I have been trying various imple...

6 20yrs

vivek.menon79

6 20yrs vivek.menon79

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