Field-Programmable Gate Arrays

Problem with SLL: "sll can not have such operands in this context" and bit-testing

I've defined this signals: signal accu : std_logic_vector(31 downto 0) := (others => '0'); signal data : integer range...

0 comments posted 20yrs

posted by fb

0 comments posted 20yrs posted by fb

Pointers for sending data using ethernet connection from V2Pro

Hi all, I am using a Xilinx V2Pro7 FF672 board. I want to send some data values using an ethernet card.(no Power PC, onl...

4 comments posted 20yrs

posted by vivek.menon79

4 comments posted 20yrs posted by vivek.menon79

Missing ISE HTML online help (pdf sucks!)

Is is just me that thinks the pdf documents suck? The html with the docsan search was just awesome! Pdf takes ages to l...

1 comments posted 20yrs

posted by mleikvol

1 comments posted 20yrs posted by mleikvol

lwIP on Xilinx Virtex 2 Pro

Hey! I am wondering if anyone has any experience from using lwIP on a Xilinx Virtex 2 Pro and the raw API? I am especial...

0 comments posted 20yrs

posted by hampus.thorellNOSPAM

0 comments posted 20yrs posted by hampus.thorellNOSPAM

rocketIO simulation

Does anyone have a feel for at what point rocketIO simulation becomes necessary. I have an FPGA right next to my PCIExp...

1 comments posted 20yrs

posted by colin_toogood

1 comments posted 20yrs posted by colin_toogood

Nu Horizon Xilinx 1500 fpga board

Hi, I am a Master student from UNIS and I am doing project about image processing. I am wondering if anyone have a tast...

1 comments posted 20yrs

posted by eem3kc

1 comments posted 20yrs posted by eem3kc

property of lockett

the property of jun g. lockett was now owned by unsaman, because jun lockett was surendered to unsaman when his private...

1 comments posted 20yrs

posted by utahjazz

1 comments posted 20yrs posted by utahjazz

Help on simulating ddr controler generated by MIG!!

I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct...

1 comments posted 20yrs

posted by fanhao

1 comments posted 20yrs posted by fanhao

Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?

I'm considering various options to implement a tapped delay line in an S3 device. I believe that using the carry chain...

3 comments posted 20yrs

posted by peter

3 comments posted 20yrs posted by peter

Pc and xcv200e doesn't talk,not exactly the right cable maybe..

I'm still here thanks to this newsgroup i finally built a cable III that works fine with cpld's like xc95144xl(3,3V),i...

4 comments posted 20yrs

posted by blisca

4 comments posted 20yrs posted by blisca

How to evaluate the space efficiency of a historic design.

Before I start let me say I'm not sure this is either an intelligent question nor an answerable one... so please be gen...

7 comments posted 20yrs

posted by pm940

7 comments posted 20yrs posted by pm940

Altium Designer LiveDesign Evaluation Kits (once again)

Hi all, I know this has been discussed on the NG before, but it seems like every time it is discussed someone hijacks t...

11 comments posted 20yrs

posted by burn.sir

11 comments posted 20yrs posted by burn.sir

help downloading picoblaze from xilinx

Hi, I am not able to download the Picoblaze bundle from Xilinx site. The ifulcrum questionnaire crashes on me. Any sugge...

4 comments posted 20yrs

posted by vivek.menon79

4 comments posted 20yrs posted by vivek.menon79

RS232 transmitter core--Xilinx xapp223(Chapman's macro)

I came across the Xilinx application xapp223 for the implementation of the UART cores. I have been trying various imple...

6 comments posted 20yrs

posted by vivek.menon79

6 comments posted 20yrs posted by vivek.menon79

Generic synthesis target in Synplify Pro

Hi folks I'm working with Synplify Pro (8.5.1) and I'm trying to test whether VHDL code is synthesizable. How can I do...

5 comments posted 20yrs

posted by rnbrady

5 comments posted 20yrs posted by rnbrady