Latest threads in Field-Programmable Gate Arrays

Xilinx BUFGMUX Setup Time requirement clarification needed

Hello, e.g. the XC3SE Datasheet ds312 tells on page 59 in the Clock Buffers/Multiplexers section: "As specified in DC a...

3 20yrs

bon

3 20yrs bon

Problem to extend Xilinx GSRD Design

Hi i'm using the Xilinx GSRD design. Now i try to connect a simple IP core to the reference design. The problem is that...

12 20yrs

test

12 20yrs test

Stopping the clock for power management

Hello, For a low power application I would like to stop the clock feed into a FPGA when enter ?sleep mode?. This is a c...

4 20yrs

ndf123456789

4 20yrs ndf123456789

EDK: Using DCR bus on ML310-based project

Hi, I'm working with the ML310 eval board. Is there anyone who has a working example on how to create a custom IP on the...

3 20yrs

king.azman

3 20yrs king.azman

NCO Clock driven Designs in FPGA

Hi everyone, I have a few doubts that are not being addressed in fpga groups(at least i could not find the one ) though...

3 20yrs

shuklrajeev

3 20yrs shuklrajeev

ANNC: x8 PCI Express w/ FPGA Webcast

Lattice is holding a webcast tomorrow, Thursday, June 29, "Designing FPGA-based PCI Express x1 / x4 / x8 Solutions." Th...

0 20yrs

bart.borosky

0 20yrs bart.borosky

xilinx ml423 boards available ?

Hi, I have seen mention of a board called ML423 here http://www.xilinx.com/bvdocs/userguides/ug087.pdf. Hitechglobal se...

0 20yrs

kal*

0 20yrs kal*

How to comm with Altera JTAG UART (from custom host software)?

Hi, is there any way to communicate with software running on a NIOS2 SOPC through JTAG from custom software on a Host P...

2 20yrs

kawk

2 20yrs kawk

DDR2 at 125MHz or lower with Cyclone2

Hello all, I am starting a brand new design, memory speed is not important (but depth is). This is my first time design...

2 20yrs

visualfor

2 20yrs visualfor

Virtex5 Availability

Can anyone tell me the true availability of Xilinx Virtex5 Engineering samples ? I have talked to distributors who say...

5 20yrs

jeffnewcomb

5 20yrs jeffnewcomb

Synplify prepending Z's to top level signal names in Verilog

Hi, Does anyone know of a way to stop Synplify from pre-pending a "Z" to names of top-level entity I/O signals which beg...

3 20yrs

jacob.bower

3 20yrs jacob.bower

Spartan 3E, Output File

I'm using all Xilinx tools, namely ISE WebPACK. So I am to the point where I've got my VHDL written, and when I send th...

1 20yrs

alexmchale

1 20yrs alexmchale

Reverse engineering has the protection of law in the U.S.

Hi, Do you know "reverse engineering has the protection of law"? A good paper in http://www.fpgajournal.com/articles_20...

2 20yrs

wtxwtx

2 20yrs wtxwtx

Spartan3e starter kit vga mod

I have added some notes to www.fpgaarcade.com describing how to modify the Spartan kit board to have 12 bit RGB output...

8 20yrs

mikej

8 20yrs mikej

PLB IPIF Master Read Failure

I have been reading everyone's comments on how to setup a Master Read, but I have hit a wall. I can make the Read Reque...

0 20yrs

andrewgschmidt

0 20yrs andrewgschmidt