Altium Designer LiveDesign Evaluation Kits (once again)

I belive that the basic purpose of these boards is to offer a platform for Altium Designer (software) evaluation. So, if you are an interested company, you buy a couple of these cheapos and recive a 30-day Designer Licence for your engineers to play with it. Then they are supposed to be thrilled and then you buy them NanoBoards and pay for Designer licences (not cheapos). But on the other hand, the NanoBoard isn't that much better, so you should be able to similar designs with the eval board...

Not sure 'bout that... I belive all the programming is done via JTAG, if that means anything to you... Maybe you could resolder the cable to work with different programmers if it doesn't by default?

That would be the Altium Designer licence.

AFAIK, the supplied FPGA's are RAM-based, so you would have to "reburn" your whole design anyway... The purpose of these boards is to do live design, I belive. Not sure 'bout flash, though.

This is all I know, hope this helps a bit.

Regards,

- R.

Hi,

I own the Cyclone one and I'm very happy with it; can't tell about the Xilinx version.

The Cyclone board has a 2x13 pin header to connect to a PC's parallel port. It then behaves as if you used a ByteBlaster-compatible cable in JTAG mode . It works with Alteras Quartus and NIOS IDE out of the box. NIOS IDE complains that you should use an USB Blaster Rev.B for better compatibility, but I haven't had any problems with the parallel cable. With some rewiring you can attach an USB Blaster as well (see below).

No.

Yes, there is no configuration device. The pads of the FPGA that would be used to connect it to an EPCS device are tied to ground (and out of reach under the BGA).

You can remove/switch the cable without interrupting operation on the board.

The kits from Altera usually have some more connectors, interfaces with drivers (USB, Ethernet), RAM (SDRAM, not only SRAM) and Flash memory.

1MB of SRAM is okay if you want to run small programs or RTOS like uC/OS2 or RTEMS, but it isn't sufficient for larger OS like uClinux.

I have a picture with a Cyclone board with an air-wired Ethernet PHY, USB device interface (ISP1106-based, logic from OpenCores.org) and USB-Blaster-compatible interface pictured here:

It runs RTEMS on NIOS2. But it has to be reconfigured from host after each power up and therefore is really only suitable for development, not as a standalone device.

Regards, Kolja

--
mr. kolja waschk - haubach-39 - 22765 hh - germany
fon +49 40 889130-34 - fax -35 - http://www.ixo.de

If you buy the Nanoboard, you can get plug-in FPGA modules for both Altera and Xilinx devices. You also have on-board configuration flash, if you require that.

Using Altium's software, you can seamlessly target the same design to both Altera and Xilinx devices, something which I've actually done.

What sort of designs will you be "playing" with?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

The altium boards are intended to work wit their tools. Their tools means the Altium designer, which uses the Altera and Xilinx web edition as driver. The altium designer produces a netlist or sort of that goes through the Altera/Xilinx tools. While the Altium designer has multiple cores, they are supported with compiler and source line debugger. The NIOS can be loaded, I assume, as blackbox, not as processor core. Meaning there won't be a compiler for it, nor a sourceline debugger. Having a look at both solutions may be worth the time. The cost are not necessarily that high when put in comparison to the overall project cost and the saved time.

Rene

--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Actually, no - the boards are quite generic. They just don't have local configuration memories on them. They should be quite usable as development boards even if you decide not to license the Altium software. Even Altium mentions that the boards are usable with the ordinary tools on their website (which is why the boards are $99 and you get to keep them)

Although I have since decided to go with another board, it should be possible to attach a PLD to the "printer port" header, and load the board with an SVF player (or equivalent for Altera) via JTAG.

radarman schrieb:

its easier to convert SVF to ACE format using Xilinx tools (SVF2ACE) and make the PLD to play pack ACE file :)

way simpler an ACE Player requires only

32 bit count register 3 - 8 bit registers (can be one if verify is not supported) one command register (can be 3 bits only) simple state machine

additional some logic to hold the address logic for external memory

no problem for a smallest micro or 128 macrocell PLD

ASFAIK all other JTAG bytecode players require more resources

Antti

Antti, Could you point me to some more info on the ACE format and players? The only info I seem to be able to dig up is on SystemACE - the Xilinx CF reader. This sounds like a good use for a smallish CPLD, and something I can try out on my Digilent XC2XL board.

Thanks!

-Seth

radarman schrieb:

Hi Seth,

There is no public info on the ACE format. So you have 2 options:

Choice #1: You (or anyone else) can obtain it in some time. The actual amount you would spend depends on your brain and mileage. For me the target time was about one hour. You can try obtaining this info for fun if you like using your brain. Dont feel bad if your target time is more than one hour.

or

Choice #2: Get my brain. The explanation how I used my brain may come handy now and later.

As of players - I have not implemented the player but inside the brain snapshot are ACE dump and compress utilities with full source codes, writing an player is trivial as well. Both the dump and compress utilities did take about one hour each of time to write from scratch. Note the ACE compress utility is only able to compress ACE files generated by ISE/Impact version 8.1 or earlier, if Xilinx enhances its ACE output generation in new releases of the ISE then the utility will no longer be able to compress the ACE files.

Antti

No need. XAPP139 appears to take all the mystery out of it. It appears that with careful timing, you could even use a serial platform flash with your CPLD, allowing for JTAG programmability using standard tools. You appear to still need a bit counter, though. I'm assuming that you were planning on pre-programming the size of N into the design - since each device has a different number of bits in the configuration stream.

I haven't had time to sit down and write the code yet, but an hour seems reasonable.

-Seth

radarman schrieb:

o sure an custom jtag bytecode player can sure be implemented within one hour :)

but the docu you referred only talks about jtag config, there is defenetly no mystery about that and a PLD that can configure an FPGA using JTAG from spi flash should fit into 36 macrocells.

Antti

ok, thanks for your answers everyone.

The "fun" i was talking about is the usual hobby-retro stuff. I would also like to play with microblaze/nios2 a bit.

Anyway, i still have three questions for you: 1. What is the third party thing they sell for $49? is it just a JTAG cable? 2. How does the board work with NIOS II (from what i understand, "free" pre compiled SoC exists for some development boards. does it include this one?). Or Xilinx EDK for that matter? 3. What does the nanoboard cost? What do they charge for shiping to EU? (Altium sales wouldnt answer those!).

You could mail me directly for the last one

I still think the boards are very cheap, Altera NIOS II board with the same FPGA costs $500 (ok, it has more stuff on the board, but who needs them?). Even the very cheep T-rex board is more expensive and has a smaller FPGA. Also, their software might turn out to be good [it might even be cheaper than our current development environments].

other than that, i wouldn't mind buying Antti's brain for one dollar :)

regards, -Burns