Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

An idea for a product (FPGA/ASIC based)

Folx, At work, we encode tons of video and some/most have fairly short TTM requirements. It is all Web-destined and soo...
18 comments posted 20yrs
posted by rashid.karimov
18 comments posted 20yrs posted by rashid.karimov

Data Logging / FPGA Dev board

I'm having a problem with data logging. I need to grab (and analyze) about 60 bits of data at about 120 MHz. I'm runnin...
1 comments posted 20yrs
posted by pfraser
1 comments posted 20yrs posted by pfraser

Exciting Project!

Crystal Instruments is an engineering firm, founded in 1996 and focused in the area of embedded systems, digital signal...
0 comments posted 20yrs
posted by go.ci9999
0 comments posted 20yrs posted by go.ci9999

Virtex4 Mini-Module Phy interrupt

Hi all, I have serious problems with V4FX12MM phy interrupt line. There is no indication in MiniModule User Guide that...
0 comments posted 20yrs
posted by ales.gorkic
0 comments posted 20yrs posted by ales.gorkic

Post Place and Route simulation for Microblaze....

Hi guys, I posted my problem a few days ago but I think I didn't make my points clear so I've decided to post it again....
2 comments posted 20yrs
posted by amirhossein.gholamipour
2 comments posted 20yrs posted by amirhossein.gholamipour

Need for reset in FPGAs

Hello, usually a reset signal is applied to put the FFs of an FPGA into a known state. Just some days ago I had a discu...
14 comments posted 20yrs
posted by thomas.reinemann
14 comments posted 20yrs posted by thomas.reinemann

design partition across multiple FPGAs

Hi, I am interested to learn more about techniques for design partition across multiple FPGAs. Can someone provide me wi...
3 comments posted 20yrs
posted by shalza.mittal
3 comments posted 20yrs posted by shalza.mittal

OPB or FSL?

Hi everybody, at the moment, I'm facing the decision wether to connect to a MicroBlaze through OPB or FSL. The scenario...
4 comments posted 20yrs
posted by usenet_NOSPAM_
4 comments posted 20yrs posted by usenet_NOSPAM_

EDK adding custom vhdl with multiple arch/entity

Hello, Im making a custom ip for edk. It generates x.vhd and user_logic.vhd. You are supposed to design in the user_log...
1 comments posted 20yrs
posted by None
1 comments posted 20yrs posted by None

PLB slaves

Can we have 2 separate plb slaves in one IP ? I am trying to fit 2 slaves in one peripheral . I am not using IPIF . I h...
1 comments posted 20yrs
posted by nitesh.guinde
1 comments posted 20yrs posted by nitesh.guinde

Separate enable on address for ram blocks

I am reworking a design I did a couple of years ago to fit a newer part. The original design made use of async ram bloc...
5 comments posted 20yrs
posted by spamgoeshere4
5 comments posted 20yrs posted by spamgoeshere4

Cyclone II Power Measurement on DE2 Board

I have a DE2 board with Cyclone II FPGA EP2C35F672C6. I want to measure the power consumed by my design in the FGPA dev...
0 comments posted 20yrs
posted by syzygy01
0 comments posted 20yrs posted by syzygy01