design partition across multiple FPGAs

Have a look at BYO partitioning software

Hans

Traditionally people have tried to come up with auto-partitioners that are somehow smart enough to split up connections between chips. The scope of that problem is too large. I propose you do it this way:

First, you have to define a dataset as partitionable. You cannot break apart objects unless they are connected by this specific dataset that is allowed to be broken. You'll need some communication core that goes with that dataset on both ends of the transfer. Then your partition software will automatically insert those communication cores in after it decides to separate a certain line with the breakable dataset. Um. I'm not sure I'm describing this very well. Does that make sense?

So for example, suppose you have a dataset that is made of some data bits, an enable bit, a clock, and a busy signal going the opposite direction. That dataset is breakable because you can send the data, clock, and enable to a fifo on the far chip; that fifo can send back an almost busy signal to stop data from being sent. A simpler case would be a control line that is stable ages before it is needed; your separation objects for those will just be buffers and pads.

Synplicity has a product designed for ASIC verification using FPGAs that can semi-automate the partitioning problem. I have no experience with the product.

Andy

Brann> > I am interested to learn more about techniques for design partition