HI,
I have MIG 1.5 installed and want to test the K4T51083QC-ZCD5 Samsung DDR2 chips wich reside on our FPGA prototyping board. However it seems that MIG does not support any RAM chips beside Micron ones. Does anybody know if is possible to manipulte the output files to support the chip above? Are there plans from xilinx so support additional chips in the future? When?
Any other options? I saw a DDR controller on opencores.org but no DDR2.
I don't have the Samsung datasheet, but there will be a Micron equivalent. Choose that chip when generating the MIG controller. There will be a parameter file generated as part of the design. You can fine tune any parameters there if needed.
If you're targeting Virtex 4, MIG1.5 DDR2 uses the FIFO16. You'll want to fix the read/write address FIFO. I used CoreGen to make a blockram FIFO, but Xilinx has an app note on FIFO16 workarounds. I found that under certain conditions, the controller would have 'runaway' read cycles, where the controller thought that the FIFO still had addressess to read from so it would constantly read from the same location.
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