Field-Programmable Gate Arrays

EDK - Debugging software applications located in ISOCM

According to Xilinx AR #22942 ISOCM should be readable from XMD in V4. However, this doesn't seem to be the case... Has...

1 comments posted 20yrs

posted by mbmsv

1 comments posted 20yrs posted by mbmsv

ADC08D1500 + Virtex-4

Has anyone worked with national instruments ADC08D1500 development board?? This board has a Virtex-4 FPGA that does som...

0 comments posted 20yrs

posted by vivek.menon79

0 comments posted 20yrs posted by vivek.menon79

Universal Scan with Xilinx's ML403

Hi, Does anyone have experience using Universal Scan to program the flash on Xilinx's ML403? Universal Scan should use...

2 comments posted 20yrs

posted by George.Y.Ma

2 comments posted 20yrs posted by George.Y.Ma

Routing Information of Xilinx's Virtex-II FPGA

Hi All, I am seeking for following information regarding Virtex-II FPGA: 1. Is it possible to know exact delay informat...

0 comments posted 20yrs

posted by manoj.rajpoot

0 comments posted 20yrs posted by manoj.rajpoot

Raggedstone1 Ethernet Modules Available

Finally we have the ethernet modules in stock that lots of you are asking for. Apologies to those of you that have been...

0 comments posted 20yrs

posted by removethisthenleavejea

0 comments posted 20yrs posted by removethisthenleavejea

Spartan 3E starter kit DDR SDRAM code

Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter kit? http://www.xilinx.com/xlnx/xebiz/design...

3 comments posted 20yrs

posted by fb

3 comments posted 20yrs posted by fb

Micorblaze post place and route simulation...

Hi guys, I'm trying to do post place and route simulation and generate vcd file to estimate the power with XPower. I tr...

5 comments posted 20yrs

posted by amirhossein.gholamipour

5 comments posted 20yrs posted by amirhossein.gholamipour

reprogram xcf08 serial prom without jtag

All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to...

1 comments posted 20yrs

posted by someone

1 comments posted 20yrs posted by someone

Help with RBT file

Hi guys!!! am working on a VIRETX-II FPGA and i am downloading the bit file by using the RBT File. i am now trying to d...

4 comments posted 20yrs

posted by harissh77

4 comments posted 20yrs posted by harissh77

micron Flash controller VHDL disappeared ??

Hi Xilinx XCELL (First Quarter 2006) has an articel that says that the VHDL code is available from Micron website http:...

1 comments posted 20yrs

posted by Antti.Lukats

1 comments posted 20yrs posted by Antti.Lukats

Can't get my Verilog Peripheral to import into XPS! Any tricks?

Hello - I am trying to write a custom peripheral using Verilog and version 8.1 of the Xilinx tool kits (ISE and XPS). I...

7 comments posted 20yrs

posted by jhouse

7 comments posted 20yrs posted by jhouse

Binary Counter Core

Hello everyone, I have ISE Foundation 7.1 and I've downloaded a standalone CoreGEN, but they don't give me an option fo...

7 comments posted 20yrs

posted by

7 comments posted 20yrs posted by

Diffenrential I/Os in Virtex-4

Hi *, I'm having some issues understanding certain limitations regarding differential inputs/outputs: 1. In the "Virtex...

6 comments posted 20yrs

posted by smd

6 comments posted 20yrs posted by smd

Low cost SMD Oven for making SMD samples and Prototypes

This SMD Oven Controller (SMDOC-01) is designed to use with a toaster oven. It provide a low cost solution for making S...

0 comments posted 20yrs

posted by erica

0 comments posted 20yrs posted by erica

how to implement multi-port memory

hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write p...

8 comments posted 20yrs

posted by pasacco

8 comments posted 20yrs posted by pasacco