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Post Place and Route simulation for Microblaze....

Hi guys, I posted my problem a few days ago but I think I didn't make my points clear so I've decided to post it again. I have a very simple Microblaze based system which just has the processor and LMB BRAMs for instruction and data. I'm running my code on this system and I basically want to measure the power consumption of the system. I've generated a .vcd file by behavioral simulation of my design and estimated the power with that. But it seems that it is far unrealistic. As well by behavioral simulation I could verify my system behavior. I was monitoring my ilmb_lmb_abus which was the address bus of the instruction port of the microblaze and on the other hand I had the assembly code of my software so I could see what's going on in the system. However now to get a better estimation of power consumption of my system I want to do Post Place and Route simulation and generate the .vcd by doing so. I've made sure that there is data in BRAMs in system_stub_timesim.vhd file generated by ISE. But when modelsim simulates my design I observe irregular fetches on my address bus. Even the contents of the addresses which should be the opcodes of the instructions doesn't match with the assembly file that I have. I'm also monitoring Program Counter value but that one too has irregular patterns in addresses though different from address bus. I'm trying to verify my simulation to make sure that the .vcd file that is generated is what it should be however I'm stuck here because I don't know what the problem is. I am wondering if any of you have any idea what is going on and what can I do about it,

I really appreciate your response and thanks alot beforehand,

Amir

PS. By the way I'm using ISE 8.1.03i and EDK 8.1.01i and Modelsim SE 6.0

Reply to
Xesium
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Hi,

There is too little information for me to give you an answer of your problem.

Can you explain a little what you mean with "irregular patterns"? Are you running simulation with the timing information file (.sdf) ?

Göran Bilski

Xesium wrote:

Reply to
Göran Bilski

Goran Bilski,

The values are reversed. If you reverse the addresses then you get the correct values. MicroBlaze uses 0:31 but I think that you are watching the values in the other order 31:0

G=F6ran

-----Original Message----- From: Xesium [mailto: snipped-for-privacy@gmail.com] Sent: Wednesday, July 19, 2006 15:47 To: Goran Bilski Subject: Re: Post Place and Route simulation for Microblaze...

Dear Goran, I double checked everything again about Post Translate and Post Place and Route simulation. If the contents of my BRAMs are all 0 I have a sequence of fetched addresses in Post Translate which is exactly the same as Post Place and Route (when the address gets stable on address bus) if the contents of my BRAMs are 0 in system_stub_timesim.vhd. On the other hand if my BRAMs are populated with data and opcodes I have the same sequence for Post Translate and Post Place and Route however the sequence is different from the case that the contents are 0. After all the both sequence of addresses are insane and not reasonable. This is the sequence of the fetched addresses when the content of my BRAMs are 0:

00000000 -> 20000000 -> 10000000 -> 30000000 -> 08000000 -> 28000000 -> 18000000 -> 38000000 -> 04000000 ...

and this is the sequence when my BRAMs are populated with data:

00000000 -> 20000000 -> 10000000 -> 0A000000 -> 2A000000 -> 1A000000 -> 3A000000 -> 06000000 ...

considering my address space which is 00000000 - 0000FFFF these addresses are not reasonable.

Looking forward to your advice, Thanks alot,

Amir

G=F6ran Bilski wrote:

Reply to
Xesium

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