Field-Programmable Gate Arrays

Re: Virtex 4, LVDS I/O: Sanity check please

> Standards like SSTL are good for this due to the low signal swing. The > biggest decision is if to use DCI which burn...

8 comments posted 20yrs

posted by PeterSmith1954

8 comments posted 20yrs posted by PeterSmith1954

NAND flash hangs

Please help... I'm trying to access a Samsung K9K4G08U0M NAND flash device with an Altera Cyclone II. The NAND flash re...

4 comments posted 20yrs

posted by baker.ea

4 comments posted 20yrs posted by baker.ea

Partial shift register extraction in ISE

Hi all, I'm building a design where I want ISE (8.1) to extract the shift registers in some parts, i.e. where I have in...

4 comments posted 20yrs

posted by xjohbex

4 comments posted 20yrs posted by xjohbex

Burnig flash image with Xilinx EDK flashwriter tool

I am using EDK 7.1 and trying to determine if the built in capabilties of the flashwriter tool will suffice for our boa...

0 comments posted 20yrs

posted by sgfallows

0 comments posted 20yrs posted by sgfallows

JED file translator

Hi all, I have a JED file for an old PAL device and I have to put this design in an EPLD. Is there a tool that can read...

2 comments posted 20yrs

posted by t

2 comments posted 20yrs posted by t

GeneXproTools 4.0 - GEP modeling tools for Math and Boolean problems

I'm proud to announce that Gepsoft is releasing today GeneXproTools 4.0, a new version of the easy and powerful predict...

0 comments posted 20yrs

posted by cferreira

0 comments posted 20yrs posted by cferreira

noob question: reset problem

Hello all I have implemented the typicall "hello world" in a spartan3 with: - 1 MBlaze. - 2 LMB buses (instructions and...

0 comments posted 20yrs

posted by fndoleon

0 comments posted 20yrs posted by fndoleon

Opencore ddr_controller

Hi, I am trying to do the post_par simulation of the opercore ddr controller(from opencore.org) There is feedback clk i...

4 comments posted 20yrs

posted by subin.82

4 comments posted 20yrs posted by subin.82

Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?

Hello Group. Quite simple question... but I cannot seem to be able to find the answer: Given a Code Image initially tar...

4 comments posted 20yrs

posted by Jesper.Kristensen

4 comments posted 20yrs posted by Jesper.Kristensen

Virtex 4, LVDS I/O: Sanity check please

I have a project where I will have a large array of V4 FPGAs. Each chip is intended to connect to its four orthogonal n...

1 comments posted 20yrs

posted by Marco

1 comments posted 20yrs posted by Marco

EDK PowerPC ISS : download errors?

Has anyone successfully used the PowerPC Instruction-Set Simulator packaged with EDK (8.1)? I can set it up and launch...

7 comments posted 20yrs

posted by

7 comments posted 20yrs posted by

OpenFire - public domain MicroBlaze clone in verilog

Hi google really finds things: http://www.ccm.ece.vt.edu/~amarschn/openfire/tools.html at the above link you can downlo...

7 comments posted 20yrs

posted by Antti.Lukats

7 comments posted 20yrs posted by Antti.Lukats

FPGA consultants

We are looking for a consultant for a project that involves an FPGA to implement our data manipulation algorithm to sca...

1 comments posted 20yrs

posted by hrocarina

1 comments posted 20yrs posted by hrocarina

2048 input or gate ?

Hi everyone, I am trying to 'or' a 2K vector in Virtex4. Looking at the problem as a first approximation, it would need...

19 comments posted 20yrs

posted by kal*

19 comments posted 20yrs posted by kal*

Xilinx System ACE Player available

Hi http://www.xilant.com/downloads/aceplayer_1_0.zip small utility to play back Xilinx ACE files can be used to test th...

0 comments posted 20yrs

posted by Antti.Lukats

0 comments posted 20yrs posted by Antti.Lukats