Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

Which PCI core for Cyclone II board?

Does anyone have experience with more than one of the PCI cores out there? I'm working a PCI card that's still in the e...
19 comments posted 20yrs
posted by brian.mcf1985
19 comments posted 20yrs posted by brian.mcf1985

Re: Virtex 4, LVDS I/O: Sanity check please

> Standards like SSTL are good for this due to the low signal swing. The > biggest decision is if to use DCI which burn...
8 comments posted 20yrs
posted by PeterSmith1954
8 comments posted 20yrs posted by PeterSmith1954

NAND flash hangs

Please help... I'm trying to access a Samsung K9K4G08U0M NAND flash device with an Altera Cyclone II. The NAND flash re...
4 comments posted 20yrs
posted by baker.ea
4 comments posted 20yrs posted by baker.ea

Partial shift register extraction in ISE

Hi all, I'm building a design where I want ISE (8.1) to extract the shift registers in some parts, i.e. where I have in...
4 comments posted 20yrs
posted by xjohbex
4 comments posted 20yrs posted by xjohbex

JED file translator

Hi all, I have a JED file for an old PAL device and I have to put this design in an EPLD. Is there a tool that can read...
2 comments posted 20yrs
posted by t
2 comments posted 20yrs posted by t

noob question: reset problem

Hello all I have implemented the typicall "hello world" in a spartan3 with: - 1 MBlaze. - 2 LMB buses (instructions and...
0 comments posted 20yrs
posted by fndoleon
0 comments posted 20yrs posted by fndoleon

Opencore ddr_controller

Hi, I am trying to do the post_par simulation of the opercore ddr controller(from opencore.org) There is feedback clk i...
4 comments posted 20yrs
posted by subin.82
4 comments posted 20yrs posted by subin.82

Virtex 4, LVDS I/O: Sanity check please

I have a project where I will have a large array of V4 FPGAs. Each chip is intended to connect to its four orthogonal n...
1 comments posted 20yrs
posted by Marco
1 comments posted 20yrs posted by Marco

EDK PowerPC ISS : download errors?

Has anyone successfully used the PowerPC Instruction-Set Simulator packaged with EDK (8.1)? I can set it up and launch...
7 comments posted 20yrs
posted by
7 comments posted 20yrs posted by

OpenFire - public domain MicroBlaze clone in verilog

Hi google really finds things: http://www.ccm.ece.vt.edu/~amarschn/openfire/tools.html at the above link you can downlo...
7 comments posted 20yrs
posted by Antti.Lukats
7 comments posted 20yrs posted by Antti.Lukats

FPGA consultants

We are looking for a consultant for a project that involves an FPGA to implement our data manipulation algorithm to sca...
1 comments posted 20yrs
posted by hrocarina
1 comments posted 20yrs posted by hrocarina

2048 input or gate ?

Hi everyone, I am trying to 'or' a 2K vector in Virtex4. Looking at the problem as a first approximation, it would need...
19 comments posted 20yrs
posted by kal*
19 comments posted 20yrs posted by kal*