Dear all, I recently jumped to Quartus 6.0 (from former 5.x) and experienced that the design would not compile correctly. I am working with a Cyclone II device and (in this case) have the problems in beneath a controller for an AD-converter which is not read correctly. Doing a compilation with the former 5.x Version produces valid fpga code.
I did not contact the support for this yet because I cannot 100% describe the problem and locate the misbehaviour in the data chain. I also cannot pas away the code to let somebody else find it. Currently I am about to use signal tap to locate it, but have low time to spent on this, however.
I have similar parts of the design /channels several times in the code, and other fragments work, however. It seems to be a problem of a particular part of the FPGA code, which might not be interpreted the same way in the both versions.
Anybody else discovered genereal probs with the new 6.0 of Quartus?