I am having several dual port block rams in a cyclone II device. The access takes place as simple dual port option with only one clock for the bram but sometimes a write, when a read is done simultaneously. I expexted the old data to appear at the output as demanded, when I defined the brams from within the altera megafunction wizzard.
I know about the possible bugs, when using two different clocks, as described in an altera technical announcement, therefore I use only one system clock for the rams.
I observe corrupted data though! :-( It obviously is caused when the reading and writing processes access the same time. I am sure that I contraint "old data" and varified this in the vhdl-definitions created be the wizzard.